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Message-Id: <169975054631.11360.10958982747975281844.git-patchwork-notify@kernel.org>
Date: Sun, 12 Nov 2023 00:55:46 +0000
From: patchwork-bot+linux-riscv@...nel.org
To: Anup Patel <apatel@...tanamicro.com>
Cc: linux-riscv@...ts.infradead.org, pbonzini@...hat.com,
atishp@...shpatra.org, palmer@...belt.com,
paul.walmsley@...ive.com, conor@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, shuah@...nel.org,
ajones@...tanamicro.com, mchitale@...tanamicro.com,
devicetree@...r.kernel.org, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-kselftest@...r.kernel.org
Subject: Re: [PATCH v3 0/6] KVM RISC-V Conditional Operations
Hello:
This series was applied to riscv/linux.git (fixes)
by Anup Patel <anup@...infault.org>:
On Tue, 3 Oct 2023 09:22:20 +0530 you wrote:
> This series extends KVM RISC-V to allow Guest/VM discover and use
> conditional operations related ISA extensions (namely XVentanaCondOps
> and Zicond).
>
> To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
> branch at: https://github.com/avpatel/kvmtool.git
>
> [...]
Here is the summary with links:
- [v3,1/6] dt-bindings: riscv: Add Zicond extension entry
https://git.kernel.org/riscv/c/00c6f39c8247
- [v3,2/6] RISC-V: Detect Zicond from ISA string
https://git.kernel.org/riscv/c/662a601aa355
- [v3,3/6] RISC-V: KVM: Allow Zicond extension for Guest/VM
https://git.kernel.org/riscv/c/df68f4d8cb49
- [v3,4/6] KVM: riscv: selftests: Add senvcfg register to get-reg-list test
https://git.kernel.org/riscv/c/4d554e0226e6
- [v3,5/6] KVM: riscv: selftests: Add smstateen registers to get-reg-list test
https://git.kernel.org/riscv/c/e1a8db0c9a0e
- [v3,6/6] KVM: riscv: selftests: Add condops extensions to get-reg-list test
https://git.kernel.org/riscv/c/2b3f2b78ec93
You are awesome, thank you!
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