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Message-Id: <20231112061514.2306187-36-guoren@kernel.org>
Date:   Sun, 12 Nov 2023 01:15:11 -0500
From:   guoren@...nel.org
To:     arnd@...db.de, guoren@...nel.org, palmer@...osinc.com,
        tglx@...utronix.de, conor.dooley@...rochip.com, heiko@...ech.de,
        apatel@...tanamicro.com, atishp@...shpatra.org, bjorn@...nel.org,
        paul.walmsley@...ive.com, anup@...infault.org, jiawei@...as.ac.cn,
        liweiwei@...as.ac.cn, wefu@...hat.com, U2FsdGVkX1@...il.com,
        wangjunqiang@...as.ac.cn, kito.cheng@...ive.com,
        andy.chiu@...ive.com, vincent.chen@...ive.com,
        greentime.hu@...ive.com, wuwei2016@...as.ac.cn, jrtc27@...c27.com,
        luto@...nel.org, fweimer@...hat.com, catalin.marinas@....com,
        hjl.tools@...il.com
Cc:     linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, Guo Ren <guoren@...ux.alibaba.com>
Subject: [RFC PATCH V2 35/38] clocksource: riscv: s64ilp32: Use __riscv_xlen instead of CONFIG_32BIT

From: Guo Ren <guoren@...ux.alibaba.com>

When s64ilp32 enabled, CONFIG_32BIT=y but __riscv_xlen=64. So we
must use __riscv_xlen to detect real machine XLEN for CSR access.

Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Signed-off-by: Guo Ren <guoren@...nel.org>
---
 drivers/clocksource/timer-riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index da3071b387eb..fe83b4e2005a 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -38,7 +38,7 @@ static int riscv_clock_next_event(unsigned long delta,
 
 	csr_set(CSR_IE, IE_TIE);
 	if (static_branch_likely(&riscv_sstc_available)) {
-#if defined(CONFIG_32BIT)
+#if __riscv_xlen == 32
 		csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
 		csr_write(CSR_STIMECMPH, next_tval >> 32);
 #else
-- 
2.36.1

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