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Message-ID: <f4551a7a-61e6-4d97-94c2-da2e4e9e8cb3@starfivetech.com>
Date: Mon, 13 Nov 2023 17:42:05 +0800
From: William Qiu <william.qiu@...rfivetech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-pwm@...r.kernel.org>
CC: Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Uwe Kleine-König <u.kleine-koenig@...gutronix.de>,
Hal Feng <hal.feng@...rfivetech.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
"Palmer Dabbelt" <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Subject: Re: [PATCH v7 1/4] dt-bindings: pwm: Add OpenCores PWM module
On 2023/11/10 20:24, Krzysztof Kozlowski wrote:
> On 10/11/2023 07:20, William Qiu wrote:
>> Add documentation to describe OpenCores Pulse Width Modulation
>> controller driver.
>>
>> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
>> ---
>> .../bindings/pwm/opencores,pwm.yaml | 56 +++++++++++++++++++
>> 1 file changed, 56 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>> new file mode 100644
>> index 000000000000..8f776bbc1112
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>> @@ -0,0 +1,56 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: OpenCores PWM controller
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@...rfivetech.com>
>> +
>> +description:
>> + OpenCores PTC ip core contains a PWM controller. When operating in PWM mode, the PTC core
>> + generates binary signal with user-programmable low and high periods. All PTC counters and
>> + registers are 32-bit.
>
> Wrap at 80 (as Coding Style asks)
>
Will update.
>> +
>> +allOf:
>> + - $ref: pwm.yaml#
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - items:
>> + - enum:
>> + - starfive,jh7100-pwm
>> + - starfive,jh7110-pwm
>> + - const: opencores,pwm
>
> That's a very, very generic compatible. Are you sure, 100% sure, that
> all designs from OpenCores from now till next 100 years will be 100%
> compatible?
>
My description is not accurate enough, this is OpenCores PTC IP, and PWM
is one of those modes, so it might be better to replace compatible with
"opencores, ptc-pwm"
What do you think?
Best Regrads,
William
>
> Best regards,
> Krzysztof
>
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