linux-kernel - Re: [PATCH 4/4] riscv: dts: sophgo: add reset phandle to all uart nodes

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Sun, 12 Nov 2023 21:04:55 -0500
From:   Samuel Holland <samuel.holland@...ive.com>
To:     Jisheng Zhang <jszhang@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Chao Wei <chao.wei@...hgo.com>,
        Chen Wang <unicorn_wang@...look.com>
Subject: Re: [PATCH 4/4] riscv: dts: sophgo: add reset phandle to all uart
 nodes

Hi Jisheng,

On 2023-11-12 6:55 PM, Jisheng Zhang wrote:
> Although, the resets are deasserted by default. Add them for
> completeness.
> 
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> ---
>  arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index 4032419486be..e04df04a91c0 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -4,6 +4,7 @@
>   */
>  
>  #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset/sophgo,cv1800b-reset.h>
>  
>  / {
>  	compatible = "sophgo,cv1800b";
> @@ -65,6 +66,7 @@ uart0: serial@...0000 {
>  			reg = <0x04140000 0x100>;
>  			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&osc>;
> +			resets = <&rst RST_UART0>;

Since it's not obvious: this breaks devicetree forward compatibility. An
existing kernel will fail the devm_reset_control_get_optional_exclusive() in
8250_dw.c because it has no driver for the reset controller.

This may not be a concern yet, since the devicetree is still "in development".
But it is something to keep in mind for the future. To avoid this sort of
problem, it's best to fully model the clocks/resets/other dependencies as early
as possible, and not rely on the firmware setting anything up.

Regards,
Samuel

>  			reg-shift = <2>;
>  			reg-io-width = <4>;
>  			status = "disabled";
> @@ -75,6 +77,7 @@ uart1: serial@...0000 {
>  			reg = <0x04150000 0x100>;
>  			interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&osc>;
> +			resets = <&rst RST_UART1>;
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
>  			status = "disabled";
> @@ -85,6 +88,7 @@ uart2: serial@...0000 {
>  			reg = <0x04160000 0x100>;
>  			interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&osc>;
> +			resets = <&rst RST_UART2>;
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
>  			status = "disabled";
> @@ -95,6 +99,7 @@ uart3: serial@...0000 {
>  			reg = <0x04170000 0x100>;
>  			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&osc>;
> +			resets = <&rst RST_UART3>;
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
>  			status = "disabled";
> @@ -105,6 +110,7 @@ uart4: serial@...0000 {
>  			reg = <0x041c0000 0x100>;
>  			interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&osc>;
> +			resets = <&rst RST_UART4>;
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
>  			status = "disabled";