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Message-ID: <20231113162047.2213725-1-jisheng.teoh@starfivetech.com>
Date: Tue, 14 Nov 2023 00:20:47 +0800
From: Ji Sheng Teoh <jisheng.teoh@...rfivetech.com>
To: <conor@...nel.org>
CC: <conor+dt@...nel.org>, <devicetree@...r.kernel.org>,
<jisheng.teoh@...rfivetech.com>,
<krzysztof.kozlowski+dt@...aro.org>,
<leyfoon.tan@...rfivetech.com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <mark.rutland@....com>,
<peterz@...radead.org>, <robh+dt@...nel.org>, <tglx@...utronix.de>,
<will@...nel.org>
Subject: Re: [PATCH 1/2] perf: starfive: Add StarLink PMU support
On Mon, 13 Nov 2023 13:45:00 +0000
Conor Dooley <conor@...nel.org> wrote:
> On Mon, Nov 13, 2023 at 12:22:30PM +0800, Ji Sheng Teoh wrote:
>
> > +config STARFIVE_STARLINK_PMU
> > + depends on SOC_STARFIVE
>
> Please s/SOC/ARCH/ so I have one fewer instance to delete.
Thanks Conor, will change to ARCH_STARFIVE in v2.
>
> > + bool "StarFive StarLink PMU"
> > + help
> > + Provide support for StarLink Performance Monitor Unit.
> > + StarLink Performance Monitor Unit integrates one or
> > more cores with
> > + an L3 memory system. The L3 cache events are added into
> > perf event
> > + subsystem, allowing monitoring of various L3 cache perf
> > events.
>
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