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Message-Id: <1700051821-1087-1-git-send-email-quic_msarkar@quicinc.com>
Date: Wed, 15 Nov 2023 18:06:58 +0530
From: Mrinmay Sarkar <quic_msarkar@...cinc.com>
To: agross@...nel.org, andersson@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
konrad.dybcio@...aro.org, mani@...nel.org, robh+dt@...nel.org
Cc: quic_shazhuss@...cinc.com, quic_nitegupt@...cinc.com,
quic_ramkri@...cinc.com, quic_nayiluri@...cinc.com,
dmitry.baryshkov@...aro.org, robh@...nel.org,
quic_krichai@...cinc.com, quic_vbadigan@...cinc.com,
quic_parass@...cinc.com, quic_schintav@...cinc.com,
quic_shijjose@...cinc.com,
Mrinmay Sarkar <quic_msarkar@...cinc.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org
Subject: [PATCH v3 0/3] arm64: qcom: sa8775p: add cache coherency support for SA8775P
In a multiprocessor system cache snooping maintains the consistency
of caches. Snooping logic is disabled from HW on this platform.
Cache coherency doesn’t work without enabling this logic.
This series is to enable cache snooping logic in both RC and EP
driver and add the "dma-coherent" property in dtsi to support
cache coherency in 8775 platform.
To verify this series we required [1]
[1] https://lore.kernel.org/all/1699669982-7691-1-git-send-email-quic_msarkar@quicinc.com/
v2 -> v3:
- update commit message(8755 -> 8775).
v1 -> v2:
- update cover letter with explanation.
- define each of these bits and ORing at usage time rather than
directly writing value in register.
Mrinmay Sarkar (3):
PCI: qcom: Enable cache coherency for SA8775P RC
PCI: qcom-ep: Enable cache coherency for SA8775P EP
arm64: dts: qcom: sa8775p: Mark PCIe controller as cache coherent
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 +
drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 ++++++++++
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
3 files changed, 24 insertions(+)
--
2.7.4
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