linux-kernel - Re: [PATCH v2] dt-bindings: mmc: arasan,sdci: Add gate property for Xilinx platforms

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Wed, 15 Nov 2023 16:51:37 +0100
From:   Ulf Hansson <ulf.hansson@...aro.org>
To:     Sai Krishna Potthuri <sai.krishna.potthuri@....com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Michal Simek <michal.simek@...inx.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, git@....com, saikrishna12468@...il.com
Subject: Re: [PATCH v2] dt-bindings: mmc: arasan,sdci: Add gate property for
 Xilinx platforms

On Tue, 14 Nov 2023 at 11:23, Sai Krishna Potthuri
<sai.krishna.potthuri@....com> wrote:
>
> From: Swati Agarwal <swati.agarwal@....com>
>
> Add gate property in example node for Xilinx platforms which will be used
> to ungate the DLL clock. DLL clock is required for higher frequencies like
> 50MHz, 100MHz and 200MHz.
> DLL clock is automatically selected by the SD controller when the SD
> output clock frequency is more than 25 MHz.
>
> Signed-off-by: Swati Agarwal <swati.agarwal@....com>
> Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@....com>
> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@....com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Applied for next, thanks!

Kind regards
Uffe


> ---
> Note: This patch only updates the example nodes with the gate property for
> Xilinx platforms.
>
> Changes in v2:
> - Updated subject prefix to match with the subsystem.
>
>  Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> index 3e99801f77d2..9075add020bf 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml
> @@ -226,8 +226,8 @@ examples:
>            interrupt-parent = <&gic>;
>            interrupts = <0 48 4>;
>            reg = <0xff160000 0x1000>;
> -          clocks = <&clk200>, <&clk200>;
> -          clock-names = "clk_xin", "clk_ahb";
> +          clocks = <&clk200>, <&clk200>, <&clk1200>;
> +          clock-names = "clk_xin", "clk_ahb", "gate";
>            clock-output-names = "clk_out_sd0", "clk_in_sd0";
>            #clock-cells = <1>;
>            clk-phase-sd-hs = <63>, <72>;
> @@ -239,8 +239,8 @@ examples:
>            interrupt-parent = <&gic>;
>            interrupts = <0 126 4>;
>            reg = <0xf1040000 0x10000>;
> -          clocks = <&clk200>, <&clk200>;
> -          clock-names = "clk_xin", "clk_ahb";
> +          clocks = <&clk200>, <&clk200>, <&clk1200>;
> +          clock-names = "clk_xin", "clk_ahb", "gate";
>            clock-output-names = "clk_out_sd0", "clk_in_sd0";
>            #clock-cells = <1>;
>            clk-phase-sd-hs = <132>, <60>;
> --
> 2.25.1
>