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Message-Id: <20231116053314.e976a87476cc5bc20eacde48@hugovil.com>
Date:   Thu, 16 Nov 2023 05:33:14 -0500
From:   Hugo Villeneuve <hugo@...ovil.com>
To:     Manikanta Guntupalli <manikanta.guntupalli@....com>
Cc:     <git@....com>, <michal.simek@....com>, <jacmet@...site.dk>,
        <gregkh@...uxfoundation.org>, <jirislaby@...nel.org>,
        <linux-serial@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <corbet@....net>, <christophe.leroy@...roup.eu>,
        <rdunlap@...radead.org>, <airlied@...hat.com>,
        <ogabbay@...nel.org>, <linux-doc@...r.kernel.org>,
        <radhey.shyam.pandey@....com>, <srinivas.goud@....com>,
        <shubhrajyoti.datta@....com>, <manion05gk@...il.com>
Subject: Re: [PATCH V3 1/2] Documentation: devices.txt: Update ttyUL major
 number allocation details

On Thu, 16 Nov 2023 12:59:14 +0530
Manikanta Guntupalli <manikanta.guntupalli@....com> wrote:

Hi,

> Describe when uartlite driver uses static/dynamic allocation for major
> number based on maximum number of uartlite serial ports.
> 
> Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@....com>
> ---
> Changes for V2:
> This patch introduced in V2.
> Changes for V3:
> Fix typo.
> Move description to above of ttyUL.
> ---
>  Documentation/admin-guide/devices.txt | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/admin-guide/devices.txt b/Documentation/admin-guide/devices.txt
> index 839054923530..ae7431e317ad 100644
> --- a/Documentation/admin-guide/devices.txt
> +++ b/Documentation/admin-guide/devices.txt
> @@ -2704,6 +2704,9 @@
>  		    ...
>  		 185 = /dev/ttyNX15		Hilscher netX serial port 15
>  		 186 = /dev/ttyJ0		JTAG1 DCC protocol based serial port emulation
> +
> +		 If maximum number of uartlite serial ports are more than 4, then driver uses

"are more" -> "is more"

"then driver" -> "the driver" (or "then the driver")

Hugo.


> +		 dynamic allocation instead of static allocation for major number.
>  		 187 = /dev/ttyUL0		Xilinx uartlite - port 0
>  		    ...
>  		 190 = /dev/ttyUL3		Xilinx uartlite - port 3
> -- 
> 2.25.1
> 


-- 
Hugo Villeneuve <hugo@...ovil.com>

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