linux-kernel - Re: [PATCH 3/5] dt-bindings: clock: sophgo: Add SG2042 bindings

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <MA0P287MB033225C00657712137176D22FEB7A@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM>
Date:   Fri, 17 Nov 2023 08:34:18 +0800
From:   Chen Wang <unicorn_wang@...look.com>
To:     Rob Herring <robh@...nel.org>, Chen Wang <unicornxw@...il.com>
Cc:     aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
        palmer@...belt.com, paul.walmsley@...ive.com,
        richardcochran@...il.com, sboyd@...nel.org,
        devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        haijiao.liu@...hgo.com, xiaoguang.xing@...hgo.com
Subject: Re: [PATCH 3/5] dt-bindings: clock: sophgo: Add SG2042 bindings


On 2023/11/17 2:18, Rob Herring wrote:
> On Mon, Nov 13, 2023 at 09:19:31PM +0800, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@...look.com>
>>
>> Add bindings for the clock generator on the SG2042 RISC-V SoC.
>>
>> Signed-off-by: Chen Wang <unicorn_wang@...look.com>
>> ---
>>   .../clock/sophgo/sophgo,sg2042-clkgen.yaml    | 48 +++++++++++++++++++
>>   1 file changed, 48 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
>> new file mode 100644
>> index 000000000000..e372d5dca5b9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
>> @@ -0,0 +1,48 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Sophgo SG2042 Clock Generator
>> +
>> +maintainers:
>> +  - Chen Wang <unicorn_wang@...look.com>
>> +
>> +properties:
>> +  compatible:
>> +    const: sophgo,sg2042-clkgen
>> +
>> +  system-ctrl:
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      - items:
>> +          - description: phandle to System Register Controller syscon node.
>> +    description:
>> +      The phandle to System Register Controller syscon node.
> Forget what I just said about syscon.yaml...
>
> You don't need a phandle here. Just make this node a child of the
> syscon.
Yes, making this node a child of syscon is a better solution and then we 
need not a phandle here.
> However, why do you need a child at all? Just add 'clocks' and
> '#clock-cells' to the parent directly. You don't need a child node when
> there's only 1 child node. Maybe there's other functions, but I have no
> visibility into that. IOW, define what all the functions are so we can
> provide better guidance.

The syscon is a module in SG2042 that provides multipile functions, and 
clock control is just one of them. I will add more other functions's 
nodes later under the syscon in coming patches, such as reset, pinctrl etc.

>
> Rob