linux-kernel - Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <247f4654-ec65-4857-8b35-1a79088e8b87@linaro.org>
Date:   Fri, 17 Nov 2023 11:41:02 +0100
From:   neil.armstrong@...aro.org
To:     Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Tengfei Fan <quic_tengfan@...cinc.com>, agross@...nel.org,
        andersson@...nel.org, konrad.dybcio@...aro.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        tglx@...utronix.de
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, -cc=kernel@...cinc.com
Subject: Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

On 17/11/2023 11:29, Dmitry Baryshkov wrote:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
>> thus skip pcie_1_phy_aux_clk input clock to GCC.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@...cinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 ++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> index 202b979da8ca..3aca0a433a00 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> @@ -393,6 +393,38 @@
>>       };
>>   };
>> +&gcc {
>> +    clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>> +         <&pcie0_phy>,
>> +         <&pcie1_phy>,
>> +         <0>,
>> +         <&ufs_mem_phy 0>,
>> +         <&ufs_mem_phy 1>,
>> +         <&ufs_mem_phy 2>,
>> +         <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>> +};
> 
> NAK, this should go to sm8550.dtsi unless there is a good reason.

Actually this is how QRD8550 was designed, so it's fine to mimic.

Neil

> 
>> +
>> +&pcie_1_phy_aux_clk {
>> +    status = "disabled";
>> +};
>> +
>> +&pcie0 {
>> +    perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
>> +    wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
>> +
>> +    pinctrl-0 = <&pcie0_default_state>;
>> +    pinctrl-names = "default";
>> +
>> +    status = "okay";
>> +};
>> +
>> +&pcie0_phy {
>> +    vdda-phy-supply = <&vreg_l1e_0p88>;
>> +    vdda-pll-supply = <&vreg_l3e_1p2>;
>> +
>> +    status = "okay";
>> +};
>> +
>>   &pm8550b_eusb2_repeater {
>>       vdd18-supply = <&vreg_l15b_1p8>;
>>       vdd3-supply = <&vreg_l5b_3p1>;
>