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Message-ID: <CAAhSdy1Beq-Qnio3E+Am0jVQ7ECaWa1HH2A1JkWRPN5y8tsgAQ@mail.gmail.com>
Date: Fri, 17 Nov 2023 18:34:27 +0530
From: Anup Patel <anup@...infault.org>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Anup Patel <apatel@...tanamicro.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Atish Patra <atishp@...shpatra.org>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Jiri Slaby <jirislaby@...nel.org>,
Conor Dooley <conor@...nel.org>,
Andrew Jones <ajones@...tanamicro.com>, kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org, linux-riscv@...ts.infradead.org,
linux-serial@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 6/9] RISC-V: Add stubs for sbi_console_putchar/getchar()
On Sat, Oct 21, 2023 at 10:05 PM Greg Kroah-Hartman
<gregkh@...uxfoundation.org> wrote:
>
> On Fri, Oct 20, 2023 at 12:51:37PM +0530, Anup Patel wrote:
> > The functions sbi_console_putchar() and sbi_console_getchar() are
> > not defined when CONFIG_RISCV_SBI_V01 is disabled so let us add
> > stub of these functions to avoid "#ifdef" on user side.
> >
> > Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> > Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
> > ---
> > arch/riscv/include/asm/sbi.h | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index 12dfda6bb924..cbcefa344417 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -271,8 +271,13 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> > unsigned long arg3, unsigned long arg4,
> > unsigned long arg5);
> >
> > +#ifdef CONFIG_RISCV_SBI_V01
> > void sbi_console_putchar(int ch);
> > int sbi_console_getchar(void);
> > +#else
> > +static inline void sbi_console_putchar(int ch) { }
> > +static inline int sbi_console_getchar(void) { return -1; }
>
> Why not return a real error, "-1" isn't that :)
As-per SBI spec, the legacy sbi_console_getchar() returns
-1 upon failure hence the code.
Refer, section 5.3 of the latest SBI spec
https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/commit-fe4562532a9cc57e5743b6466946c5e5c98c73ca/riscv-sbi.pdf
Although, the users of this function only expect a negative
value upon failure so better to return proper error code here.
I will update.
>
> thanks,
>
> greg k-h
>
> --
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Regards,
Anup
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