linux-kernel - Re: [PATCH V2] drm/panel: boe-tv101wum-nl6: Fine tune Himax83102-j02 panel HFP and HBP

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Date:   Fri, 17 Nov 2023 09:11:20 -0800
From:   Doug Anderson <dianders@...omium.org>
To:     Cong Yang <yangcong5@...qin.corp-partner.google.com>
Cc:     Sam Ravnborg <sam@...nborg.org>,
        Neil Armstrong <neil.armstrong@...aro.org>,
        Daniel Vetter <daniel@...ll.ch>,
        Hsin-Yi Wang <hsinyi@...gle.com>,
        David Airlie <airlied@...il.com>, zhouruihai@...qin.com,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2] drm/panel: boe-tv101wum-nl6: Fine tune Himax83102-j02
 panel HFP and HBP

Hi,

On Thu, Nov 16, 2023 at 7:25 PM Cong Yang
<yangcong5@...qin.corp-partner.google.com> wrote:
>
> The refresh reported by modetest is 60.46Hz, and the actual measurement
> is 60.01Hz, which is outside the expected tolerance.

Presumably you've swapped the numbers above? The value reported by
modetest is 60.01Hz and the actual measurement is 60.46Hz?

> Adjust hporch and
> pixel clock to fix it. After repair, modetest and actual measurement were
> all 60.01Hz.
>
> Modetest refresh = Pixel CLK/ htotal* vtotal, but measurement frame rate
> is HS->LP cycle time(Vblanking). Measured frame rate is not only affected
> by Htotal/Vtotal/pixel clock, also affecte by Lane-num/PixelBit/LineTime

s/affecte/affected

For me, the important part would be to explain the reason for the
difference. I assume that the DSI controller could not make the mode
that we requested exactly (presumably it's PLL couldn't generate the
exact pixel clock?). This new mode was picked to be achievable by the
DSI controller on the system that the panel is used on.


> /DSI CLK. If you use a different SOC platform mipi controller, you may
> need to readjust these parameters. Now this panel looks like it's only used
> by me on the MTK platform, so let's change this set of parameters.
>
> Fixes: 1bc2ef065f13 ("drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel")
> Signed-off-by: Cong Yang <yangcong5@...qin.corp-partner.google.com>
> ---
> Chage since V1:
>
> - Update commit message.
>
> V1: https://lore.kernel.org/all/20231110094553.2361842-1-yangcong5@huaqin.corp-partner.google.com
> ---
>  drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

As per discussion in V1, I'm OK with this.

Reviewed-by: Douglas Anderson <dianders@...omium.org>

I'll probably give it at least another week before applying in case
anyone else wants to speak up. It would be nice if you could send a V3
with a few more touchups to the commit message, especially since the
60.01 and 60.46 numbers were backward (unless I'm mistaken).


-Doug