linux-kernel - Re: [PATCH v2 10/12] pinctrl: samsung: add exynosautov920 pinctrl

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <ab17d61e-f645-9b76-962c-4ba2849c5f42@samsung.com>
Date:   Sat, 18 Nov 2023 16:43:26 +0900
From:   Jaewon Kim <jaewon02.kim@...sung.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Alim Akhtar <alim.akhtar@...sung.com>,
        Rob Herring <robh+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Tomasz Figa <tomasz.figa@...il.com>,
        Sylwester Nawrocki <s.nawrocki@...sung.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Thierry Reding <thierry.reding@...il.com>,
        Uwe Kleine-K?nig <u.kleine-koenig@...gutronix.de>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jiri Slaby <jirislaby@...nel.org>
Cc:     linux-arm-kernel@...ts.infradead.org,
        linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
        linux-pwm@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH v2 10/12] pinctrl: samsung: add exynosautov920 pinctrl


On 23. 11. 17. 19:48, Krzysztof Kozlowski wrote:
> On 17/11/2023 08:36, Jaewon Kim wrote:
>>>> The reason why I chose variable name 'combine' is that EINT registers was
>>>> separated from gpio control address. However, in exynosautov920 EINT
>>>> registers combined with GPx group. So I chose "combine" word.
>>> What does it mean "the GPx group"? Combined means the same place, the
>>> same register. I could imagine offset is 0x4, what I wrote last time.
>>>
>>> Is the offset 0x4?

If you are asking about the offset of GPIO control register and EINT 
control register, 0x4 is correct.

There is no empty space between the two register.


0x0 CON

0x4 DAT

0x8 PUD

0xc DRV

0x10 CONPDN

0x14 PUDPDN

0x18 EINT_CON

0x1c EINT_FLTCON

0x20 or 0x24 EINT_MASK (The size of FLTCON register depending on the 
number of gpio)

0x24 or 0x28 EINT_PEND


>>>
>>>
>>>> Is another reasonable word, I will change it.
>>> Why you cannot store the offset?
>>>
>>>> EINT registers related to the entire group(e.g SVC) were at the end of
>>>> the GPIO block and are now moved to 0xf000.
>>> So not in the same register, not combined?
>>>
>> Okay,
>>
>> Instead of the word combine, I will think of a better word in next version.
> I want to know answer to:
>
> "Why you cannot store the offset?"
>
I did not understand exactly what you said, but if i guess,,

you want to get rid of the offs because the value of the offs is always 
the same?

#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, offs, mask_offs, pend_offs)


Thanks

Jaewon Kim