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Message-ID: <20231118042730.2799-7-quic_c_gdjako@quicinc.com>
Date: Fri, 17 Nov 2023 20:27:30 -0800
From: Georgi Djakov <quic_c_gdjako@...cinc.com>
To: <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <will@...nel.org>, <robin.murphy@....com>,
<joro@...tes.org>
CC: <devicetree@...r.kernel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <linux-arm-kernel@...ts.infradead.org>,
<iommu@...ts.linux.dev>, <linux-kernel@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <quic_cgoldswo@...cinc.com>,
<quic_sukadev@...cinc.com>, <quic_pdaly@...cinc.com>,
<quic_sudaraja@...cinc.com>, <djakov@...nel.org>
Subject: [PATCH v2 6/6] arm64: dts: qcom: sdm845: Add DT nodes for the TBUs
Add the device-tree nodes for the TBUs (translation buffer units) that
are present on the sdm845 platforms. The TBUs can be used debug the
kernel and provide additional information when a context faults occur.
Describe the all registers, clocks, interconnects and power-domain
resources that are needed for each of the TBUs.
Signed-off-by: Georgi Djakov <quic_c_gdjako@...cinc.com>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 82 ++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index bf5e6eb9d313..5c7174415ae9 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -5000,6 +5001,7 @@ pil-reloc@94c {
apps_smmu: iommu@...00000 {
compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
+ ranges;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
@@ -5067,6 +5069,86 @@ apps_smmu: iommu@...00000 {
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ anoc_1_tbu: tbu@...c5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150c5000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>;
+ qcom,stream-id-range = <0x0 0x400>;
+ };
+
+ anoc_2_tbu: tbu@...c9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150c9000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>;
+ qcom,stream-id-range = <0x400 0x400>;
+ };
+
+ mnoc_hf_0_tbu: tbu@...cd000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150cd000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <0x800 0x400>;
+ };
+
+ mnoc_hf_1_tbu: tbu@...d1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150d1000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <0xc00 0x400>;
+ };
+
+ mnoc_sf_0_tbu: tbu@...d5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150d5000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <0x1000 0x400>;
+ };
+
+ compute_dsp_tbu: tbu@...d9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150d9000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <0x1400 0x400>;
+ };
+
+ adsp_tbu: tbu@...dd000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150dd000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>;
+ qcom,stream-id-range = <0x1800 0x400>;
+ };
+
+ anoc_1_pcie_tbu: tbu@...e1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150e1000 0x0 0x1000>;
+ reg-names = "base";
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
+ qcom,stream-id-range = <0x1c00 0x400>;
+ };
};
lpasscc: clock-controller@...14000 {
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