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Message-Id: <20231119131332.999-2-jszhang@kernel.org>
Date: Sun, 19 Nov 2023 21:13:31 +0800
From: Jisheng Zhang <jszhang@...nel.org>
To: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, Chao Wei <chao.wei@...hgo.com>,
Chen Wang <unicorn_wang@...look.com>
Subject: [PATCH 1/2] dt-bindings: nvmem: Add sophgo,efuses
Sophgo SoCs such as CV1800B come with eFuses used to store
factory-programmed data such as calibration settings for the built-in
ethernet PHY.
Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
---
.../bindings/nvmem/sophgo,efuse.yaml | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml
new file mode 100644
index 000000000000..e4ae81a1742a
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/sophgo,efuse.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/sophgo,efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SoC eFuse-based NVMEM
+
+description: |
+ Sophgo SoCs such as the CV1800B contain factory-programmed eFuses used to e.g. store
+ calibration data for the built-in ethernet PHY.
+maintainers:
+ - Jisheng Zhang <jszhang@...nel.org>
+
+allOf:
+ - $ref: nvmem.yaml#
+ - $ref: nvmem-deprecated-cells.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - sophgo,cv1800b-efuse
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description:
+ eFuse clock id.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ efuse@...0000 {
+ compatible = "sophgo,cv1800b-efuse";
+ reg = <0x3050000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&clk 1>;
+
+ ephy_txitune: ephy-txitune@24 {
+ reg = <0x24 0x4>;
+ };
+ };
+
+...
--
2.42.0
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