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Message-ID: <ZVzPSQeyVytoyuk7@hovoldconsulting.com>
Date: Tue, 21 Nov 2023 16:39:53 +0100
From: Johan Hovold <johan@...nel.org>
To: Mrinmay Sarkar <quic_msarkar@...cinc.com>
Cc: agross@...nel.org, andersson@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
konrad.dybcio@...aro.org, mani@...nel.org, robh+dt@...nel.org,
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dmitry.baryshkov@...aro.org, robh@...nel.org,
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quic_parass@...cinc.com, quic_schintav@...cinc.com,
quic_shijjose@...cinc.com,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org
Subject: Re: [PATCH v4 3/3] arm64: dts: qcom: sa8775p: Mark PCIe EP
controller as cache coherent
On Tue, Nov 21, 2023 at 09:02:41PM +0530, Mrinmay Sarkar wrote:
>
> On 11/21/2023 8:25 PM, Johan Hovold wrote:
> > On Tue, Nov 21, 2023 at 08:08:13PM +0530, Mrinmay Sarkar wrote:
> >> The PCIe EP controller on SA8775P supports cache coherency, hence add
> >> the "dma-coherent" property to mark it as such.
> > What tree is this against?
> >
> > Both controllers are already marked as dma-coherent in mainline so this
> > patch makes no sense (and the context also looks wrong).
> Yes both the RC controllers are dma-coherent and this change is for
> PCIe EP controller and it is inside pcie0_ep node.
> Actually the pcie0_ep node change is yet to apply on linux next.
> I just made this change on top of that and the same I mentioned in
> cover letter.
Ah, thanks for clarifying, and sorry for the noise.
Johan
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