linux-kernel - Re: [PATCH v3] perf vendor events riscv: add StarFive Dubhe-90 JSON file

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Message-ID: <20231121165339.2177083-1-jisheng.teoh@starfivetech.com>
Date:   Wed, 22 Nov 2023 00:53:39 +0800
From:   Ji Sheng Teoh <jisheng.teoh@...rfivetech.com>
To:     <irogers@...gle.com>
CC:     <acme@...nel.org>, <adrian.hunter@...el.com>,
        <alexander.shishkin@...ux.intel.com>, <aou@...s.berkeley.edu>,
        <jisheng.teoh@...rfivetech.com>, <jolsa@...nel.org>,
        <leyfoon.tan@...rfivetech.com>, <linux-kernel@...r.kernel.org>,
        <linux-perf-users@...r.kernel.org>,
        <linux-riscv@...ts.infradead.org>, <mark.rutland@....com>,
        <mingo@...hat.com>, <n.shubin@...ro.com>, <namhyung@...nel.org>,
        <palmer@...belt.com>, <paul.walmsley@...ive.com>,
        <peterz@...radead.org>
Subject: Re: [PATCH v3] perf vendor events riscv: add StarFive Dubhe-90 JSON file

On Tue, 21 Nov 2023 07:25:21 -0800
Ian Rogers <irogers@...gle.com> wrote:

> On Wed, Nov 8, 2023 at 11:51 PM Ji Sheng Teoh
> <jisheng.teoh@...rfivetech.com> wrote:
> >
> > StarFive's Dubhe-90 supports raw event id 0x00 - 0x22.
> > The raw events are enabled through PMU node of DT binding.
> > Besides raw event, add standard RISC-V firmware events to
> > support monitoring of firmware event.
> >
> > Example of PMU DT node:
> > pmu {
> >         compatible = "riscv,pmu";
> >         riscv,raw-event-to-mhpmcounters =
> >                 /* Event ID 1-31 */
> >                 <0x00 0x00 0xFFFFFFFF 0xFFFFFFE0 0x00007FF8>,
> >                 /* Event ID 32-33 */
> >                 <0x00 0x20 0xFFFFFFFF 0xFFFFFFFE 0x00007FF8>,
> >                 /* Event ID 34 */
> >                 <0x00 0x22 0xFFFFFFFF 0xFFFFFF22 0x00007FF8>;
> > };
> >
> > Perf stat output:
> > [root@...r]# perf stat -a \
> >         -e access_mmu_stlb \
> >         -e miss_mmu_stlb \
> >         -e access_mmu_pte_c \
> >         -e rob_flush \
> >         -e btb_prediction_miss \
> >         -e itlb_miss \
> >         -e sync_del_fetch_g \
> >         -e icache_miss \
> >         -e bpu_br_retire \
> >         -e bpu_br_miss \
> >         -e ret_ins_retire \
> >         -e ret_ins_miss \
> >         -- openssl speed rsa2048
> > Doing 2048 bits private rsa's for 10s: 39 2048 bits private RSA's in
> > 10.03s
> > Doing 2048 bits public rsa's for 10s: 1469 2048 bits public RSA's in
> > 9.47s
> > version: 3.0.10
> > built on: Tue Aug  1 13:47:24 2023 UTC
> > options: bn(64,64)
> > CPUINFO: N/A
> >                   sign    verify    sign/s verify/s
> > rsa 2048 bits 0.257179s 0.006447s      3.9    155.1
> >
> >  Performance counter stats for 'system wide':
> >
> >            3112882      access_mmu_stlb
> >              10550      miss_mmu_stlb
> >              18251      access_mmu_pte_c
> >             274765      rob_flush
> >           22470560      btb_prediction_miss
> >            3035839      itlb_miss
> >          643549060      sync_del_fetch_g
> >             133013      icache_miss
> >           62982796      bpu_br_retire
> >             287548      bpu_br_miss
> >            8935910      ret_ins_retire
> >               8308      ret_ins_miss
> >
> >       20.656182600 seconds time elapsed
> >
> > Signed-off-by: Ji Sheng Teoh <jisheng.teoh@...rfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com>
> > ---
> > Changelog:
> > v2 -> v3:
> > - Add standard RISC-V firmware event
> > - Update commit message to reflect addition of standard
> >   RISC-V firmware event.
> > v1 -> v2:
> > - Rename 'Starfive Dubhe' to 'StarFive Dubhe-90' in commit message.
> > - Rename 'starfive/dubhe' pmu-events folder to 'starfive/dubhe-90'
> > - Update MARCHID to 0x80000000db000090 in mapfile.csv
> > ---
> >  tools/perf/pmu-events/arch/riscv/mapfile.csv  |   1 +
> >  .../arch/riscv/starfive/dubhe-90/common.json  | 172
> > ++++++++++++++++++ .../riscv/starfive/dubhe-90/firmware.json     |
> > 68 +++++++ 3 files changed, 241 insertions(+)
> >  create mode 100644
> > tools/perf/pmu-events/arch/riscv/starfive/dubhe-90/common.json
> > create mode 100644
> > tools/perf/pmu-events/arch/riscv/starfive/dubhe-90/firmware.json
> >
> > diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> > b/tools/perf/pmu-events/arch/riscv/mapfile.csv index
> > c61b3d6ef616..5b75ecfe206d 100644 ---
> > a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++
> > b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -15,3 +15,4 @@
> >  #
> >  #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
> >  0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
> > +0x67e-0x80000000db000090-0x[[:xdigit:]]+,v1,starfive/dubhe-90,core
> >  
> 
> I've no problem with this approach, but dubhe-90's json files match
> dubhe-80s. Those files are available in perf-tools-next:
> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/pmu-events/arch/riscv/starfive/dubhe-80?h=perf-tools-next
> It could be useful to rebase the patch on that branch to make it
> easier to merge. As the files match you could make the regular
> expression for dubhe-80 match both of them like:
> 
> 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core
> 
> Thanks,
> Ian

Thanks Ian. The suggestion makes sense, will take it in and rebase in
v4.