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Message-ID: <9d8558ad-51ef-41a6-aa7e-b8a0b694ce95@quicinc.com>
Date: Tue, 21 Nov 2023 09:06:35 +0800
From: Tengfei Fan <quic_tengfan@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
<agross@...nel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<tglx@...utronix.de>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <-cc=kernel@...cinc.com>
Subject: Re: [PATCH 15/16] arm64: dts: qcom: sm8550-aim300: add pmic glink
port/endpoints
在 11/17/2023 6:32 PM, Dmitry Baryshkov 写道:
> On 17/11/2023 12:18, Tengfei Fan wrote:
>> Add nodes to support Type-C USB/DP functionality.
>>
>> On this platform, a Type-C redriver is added to the SuperSpeed graph.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 88 +++++++++++++++++++++-
>> 1 file changed, 87 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> index 6dc3040b9f76..f3c558dd40f1 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
>> @@ -100,7 +100,15 @@
>> reg = <1>;
>> pmic_glink_ss_in: endpoint {
>> - remote-endpoint = <&usb_1_dwc3_ss>;
>> + remote-endpoint = <&redriver_ss_out>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> +
>> + pmic_glink_sbu: endpoint {
>> + remote-endpoint = <&fsa4480_sbu_mux>;
>> };
>> };
>> };
>> @@ -519,6 +527,62 @@
>> };
>> };
>> +&i2c_master_hub_0 {
>> + status = "okay";
>> +};
>> +
>> +&i2c_hub_2 {
>> + status = "okay";
>> +
>> + typec-mux@42 {
>> + compatible = "fcs,fsa4480";
>> + reg = <0x42>;
>> +
>> + vcc-supply = <&vreg_bob1>;
>> +
>> + mode-switch;
>> + orientation-switch;
>> +
>> + port {
>> + fsa4480_sbu_mux: endpoint {
>> + remote-endpoint = <&pmic_glink_sbu>;
>> + };
>> + };
>> + };
>> +
>> + typec-retimer@1c {
>> + compatible = "onnn,nb7vpq904m";
>> + reg = <0x1c>;
>> +
>> + vcc-supply = <&vreg_l15b_1p8>;
>> +
>> + orientation-switch;
>> + retimer-switch;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> +
>> + redriver_ss_out: endpoint {
>> + remote-endpoint = <&pmic_glink_ss_in>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> +
>> + redriver_ss_in: endpoint {
>> + data-lanes = <3 2 1 0>;
>> + remote-endpoint = <&usb_dp_qmpphy_out>;
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> &gcc {
>> clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>> <&pcie0_phy>,
>> @@ -552,6 +616,16 @@
>> status = "okay";
>> };
>> +&mdss_dp0 {
>> + status = "okay";
>> +};
>> +
>> +&mdss_dp0_out {
>> + data-lanes = <0 1>;
>
> Why? Are you really limited to two lanes for DP by the hardware?
I will ask my internal colleagues to comfirm this configuration, and the
I will share the confimed result with you.
>
>> + remote-endpoint = <&usb_dp_qmpphy_dp_in>;
>> +};
>> +
>> +
>> &mdss_dsi0 {
>> vdda-supply = <&vreg_l3e_1p2>;
>> status = "okay";
>> @@ -861,6 +935,18 @@
>> status = "okay";
>> };
>> +&usb_dp_qmpphy_dp_in {
>> + remote-endpoint = <&mdss_dp0_out>;
>> +};
>> +
>> +&usb_dp_qmpphy_out {
>> + remote-endpoint = <&redriver_ss_in>;
>> +};
>> +
>> +&usb_dp_qmpphy_usb_ss_in {
>> + remote-endpoint = <&usb_1_dwc3_ss>;
>> +};
>> +
>> &xo_board {
>> clock-frequency = <76800000>;
>> };
>
--
Thx and BRs,
Tengfei Fan
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