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Message-ID: <8ffbb08a-730a-6b67-a22f-bbe009d5e2c3@quicinc.com>
Date: Tue, 21 Nov 2023 18:04:41 +0530
From: Prashanth K <quic_prashk@...cinc.com>
To: Krzysztof Kozlowski <krzk@...nel.org>, <stable@...r.kernel.org>,
Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>
CC: Mathias Nyman <mathias.nyman@...el.com>,
Tejas Joglekar <joglekar@...opsys.com>,
<linux-kernel@...r.kernel.org>, <linux-usbyy@...r.kernel.org>
Subject: Re: [PATCH v2 0/2] Add support for xhci-sg-trb-cache-size-quirk
On 20-11-23 03:00 pm, Krzysztof Kozlowski wrote:
> On 20/11/2023 06:58, Prashanth K wrote:
>> XHCI_SG_TRB_CACHE_SIZE_QUIRK was introduced in XHCI to resolve
>> XHC timeout while using SG buffers, which was seen Synopsys XHCs.
>> The support for this isn't present in DWC3 layer, this series
>> enables XHCI_SG_TRB_CACHE_SIZE_QUIRK since this is needed for
>> DWC3 controller.
>
> You keep Cc-ing incorrect mailing lists (bogus addresses). Just use
> get_maintainers.pl --no-git-fallback without changing its output.
>
> I repeated this comment multiple times to Qualcomm. It's awesome that
> Qualcomm participates so much in upstream development, I really
> appreciate this. However repeating the same comment over-and-over again,
> makes me quite tired. Can you instruct your colleagues to use b4 which
> solves this problem? If not, use script like:
> https://github.com/krzk/tools/blob/master/linux/.bash_aliases_linux#L91
> (or one of many other variants posted by multiple people on the mailing
> lists)
>
> Best regards,
> Krzysztof
>
Thanks for your comments! I accidentally added 'yy' in the USB mailing
list while configuring it. A careless mistake indeed :)
I will resend the the patch without adding the quirk (only driver
change) since this should be applicable for all the dwc3 devices.
Thanks again,
Prashanth K
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