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Message-ID: <CAJF2gTQdksCizkEtiE_wFAJGpyVOEUz4k2aCHi6mQiWieaMEnQ@mail.gmail.com>
Date: Thu, 23 Nov 2023 05:12:45 +0800
From: Guo Ren <guoren@...nel.org>
To: Yu Chien Peter Lin <peterlin@...estech.com>
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Subject: Re: [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension
On Wed, Nov 22, 2023 at 8:17 PM Yu Chien Peter Lin
<peterlin@...estech.com> wrote:
>
> xtheadpmu stands for T-Head Performance Monitor Unit extension.
> Based on the added T-Head PMU ISA string, the SBI PMU driver
> will make use of the non-standard irq source.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> ---
> Changes v2 -> v3:
> - New patch
> Changes v3 -> v4:
> - No change
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 64c3c2e6cbe0..7dcba86cfdd0 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -27,7 +27,7 @@ cpu0: cpu@0 {
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> + "zifencei", "zihpm", "xtheadpmu";
Reviewed-by: Guo Ren <guoren@...nel.org>
> #cooling-cells = <2>;
>
> cpu0_intc: interrupt-controller {
> --
> 2.34.1
>
--
Best Regards
Guo Ren
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