| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1700637042-11104-10-git-send-email-quic_cang@quicinc.com>
Date: Tue, 21 Nov 2023 23:10:40 -0800
From: Can Guo <quic_cang@...cinc.com>
To: quic_cang@...cinc.com, bvanassche@....org, mani@...nel.org,
stanley.chu@...iatek.com, adrian.hunter@...el.com,
beanhuo@...ron.com, avri.altman@....com, junwoo80.lee@...sung.com,
martin.petersen@...cle.com
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
linux-arm-msm@...r.kernel.org (open list:ARM/QUALCOMM SUPPORT),
linux-phy@...ts.infradead.org (open list:GENERIC PHY FRAMEWORK),
linux-kernel@...r.kernel.org (open list)
Subject: [PATCH v3 09/11] phy: qualcomm: phy-qcom-qmp-ufs: Use tbls_hs_max instead of tbls_hs_g4
Table tbls_hs_g4 is added to support HS Gear 4 and applied only if PHY
submode is HS_G4. In future, we are adding support for Gear 5 and higher.
To avoiding adding more tables, like tbls_hs_g5, let's use tbls_hs_max
instead of tbls_hs_g4. In addition, max_hs_gear is added to indicate the
maximum supported HS Gear of each configuration, so that we can check PHY
submode against it to tell if tbls_hs_max needs to be applied.
Signed-off-by: Can Guo <quic_cang@...cinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 49 +++++++++++++++++----------------
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index ad91f92..cae27a9 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -735,8 +735,11 @@ struct qmp_phy_cfg {
const struct qmp_phy_cfg_tbls tbls;
/* Additional sequence for HS Series B */
const struct qmp_phy_cfg_tbls tbls_hs_b;
- /* Additional sequence for HS G4 */
- const struct qmp_phy_cfg_tbls tbls_hs_g4;
+ /* Additional sequence for maximum supported HS Gear */
+ const struct qmp_phy_cfg_tbls tbls_hs_max;
+
+ /* Maximum supported HS Gear */
+ u32 max_hs_gear;
/* clock ids to be requested */
const char * const *clk_list;
@@ -839,7 +842,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G3,
.tbls = {
.serdes = msm8996_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
@@ -864,7 +867,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -879,7 +882,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
@@ -898,7 +901,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -913,7 +916,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
@@ -932,7 +935,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
@@ -960,7 +963,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G3,
.tbls = {
.serdes = sm6115_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
@@ -988,7 +991,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
@@ -1016,7 +1019,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
@@ -1031,7 +1034,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8150_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
.rx = sm8150_ufsphy_hs_g4_rx,
@@ -1050,7 +1053,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
@@ -1065,7 +1068,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8250_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
.rx = sm8250_ufsphy_hs_g4_rx,
@@ -1084,7 +1087,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -1099,7 +1102,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
@@ -1118,7 +1121,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -1133,7 +1136,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
@@ -1152,7 +1155,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets_v6,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8550_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
@@ -1235,11 +1238,11 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
if (qmp->mode == PHY_MODE_UFS_HS_B)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
qmp_ufs_lanes_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
+ if (qmp->submode == cfg->max_hs_gear)
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_max);
qmp_ufs_pcs_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
+ if (qmp->submode == cfg->max_hs_gear)
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_max);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
--
2.7.4
Powered by blists - more mailing lists