[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20231124072142.2786653-3-christoph.muellner@vrull.eu>
Date: Fri, 24 Nov 2023 08:21:39 +0100
From: Christoph Muellner <christoph.muellner@...ll.eu>
To: linux-riscv@...ts.infradead.org, linux-kselftest@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Andrew Morton <akpm@...ux-foundation.org>,
Shuah Khan <shuah@...nel.org>,
Jonathan Corbet <corbet@....net>,
Anup Patel <apatel@...tanamicro.com>,
Philipp Tomsich <philipp.tomsich@...ll.eu>,
Andrew Jones <ajones@...tanamicro.com>,
Guo Ren <guoren@...nel.org>,
Daniel Henrique Barboza <dbarboza@...tanamicro.com>,
Conor Dooley <conor.dooley@...rochip.com>,
Björn Töpel <bjorn@...osinc.com>,
Alan Stern <stern@...land.harvard.edu>,
Andrea Parri <parri.andrea@...il.com>,
Will Deacon <will@...nel.org>,
Daniel Lustig <dlustig@...dia.com>,
Peter Zijlstra <peterz@...radead.org>
Cc: Christoph Müllner <christoph.muellner@...ll.eu>
Subject: [RFC PATCH 2/5] RISC-V: Expose Ssdtso via hwprobe API
From: Christoph Müllner <christoph.muellner@...ll.eu>
This patch adds Ssdtso to the list of extensions which
are announced to user-space using te hwprobe API.
Signed-off-by: Christoph Müllner <christoph.muellner@...ll.eu>
---
Documentation/arch/riscv/hwprobe.rst | 3 +++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_riscv.c | 1 +
3 files changed, 5 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 7b2384de471f..8de3349e0ca2 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -80,6 +80,9 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Ssdtso extension is supported, as
+ in version v1.0-draft2 of the corresponding extension.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index b659ffcfcdb4..ed450c64e6b2 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -30,6 +30,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
+#define RISCV_HWPROBE_EXT_SSDTSO (1 << 7)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index c712037dbe10..c654f43b9699 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -162,6 +162,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZBB);
EXT_KEY(ZBS);
EXT_KEY(ZICBOZ);
+ EXT_KEY(SSDTSO);
#undef EXT_KEY
}
--
2.41.0
Powered by blists - more mailing lists