| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CA+V-a8tS0hE_aDEk6RwhhjjEPP-OQpg1zuRbFrK7JdHtLCUTYA@mail.gmail.com>
Date: Fri, 24 Nov 2023 14:57:15 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Yu Chien Peter Lin <peterlin@...estech.com>
Cc: acme@...nel.org, adrian.hunter@...el.com, ajones@...tanamicro.com,
alexander.shishkin@...ux.intel.com, andre.przywara@....com,
anup@...infault.org, aou@...s.berkeley.edu, atishp@...shpatra.org,
conor+dt@...nel.org, conor.dooley@...rochip.com, conor@...nel.org,
devicetree@...r.kernel.org, dminus@...estech.com,
evan@...osinc.com, geert+renesas@...der.be, guoren@...nel.org,
heiko@...ech.de, irogers@...gle.com, jernej.skrabec@...il.com,
jolsa@...nel.org, jszhang@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, locus84@...estech.com,
magnus.damm@...il.com, mark.rutland@....com, mingo@...hat.com,
n.shubin@...ro.com, namhyung@...nel.org, palmer@...belt.com,
paul.walmsley@...ive.com, peterz@...radead.org,
prabhakar.mahadev-lad.rj@...renesas.com, rdunlap@...radead.org,
robh+dt@...nel.org, samuel@...lland.org, sunilvl@...tanamicro.com,
tglx@...utronix.de, tim609@...estech.com, uwu@...nowy.me,
wens@...e.org, will@...nel.org, ycliang@...estech.com,
inochiama@...look.com
Subject: Re: [PATCH v4 01/13] riscv: errata: Rename defines for Andes
On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin
<peterlin@...estech.com> wrote:
>
> Using "ANDES" rather than "ANDESTECH" to unify the naming
> convention with directory, file names, Kconfig options
> and other definitions.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> Reviewed-by: Charles Ci-Jyun Wu <dminus@...estech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@...estech.com>
> Acked-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
> Changes v1 -> v2:
> - No change
> Changes v2 -> v3:
> - Rewrote commit message (suggested by Conor)
> Changes v3 -> v4:
> - Include Conor's Acked-by tag
> ---
> arch/riscv/errata/andes/errata.c | 10 +++++-----
> arch/riscv/include/asm/errata_list.h | 4 ++--
> arch/riscv/include/asm/vendorid_list.h | 2 +-
> arch/riscv/kernel/alternative.c | 2 +-
> 4 files changed, 9 insertions(+), 9 deletions(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Cheers,
Prabhakar
> diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
> index 197db68cc8da..d2e1abcac967 100644
> --- a/arch/riscv/errata/andes/errata.c
> +++ b/arch/riscv/errata/andes/errata.c
> @@ -18,9 +18,9 @@
> #include <asm/sbi.h>
> #include <asm/vendorid_list.h>
>
> -#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL
> -#define ANDESTECH_AX45MP_MIMPID 0x500UL
> -#define ANDESTECH_SBI_EXT_ANDES 0x0900031E
> +#define ANDES_AX45MP_MARCHID 0x8000000000008a45UL
> +#define ANDES_AX45MP_MIMPID 0x500UL
> +#define ANDES_SBI_EXT_ANDES 0x0900031E
>
> #define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1
>
> @@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void)
> * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
> * cache is controllable only then CMO will be applied to the platform.
> */
> - ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> + ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
> 0, 0, 0, 0, 0, 0);
>
> return ret.error ? 0 : ret.value;
> @@ -43,7 +43,7 @@ static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
> if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))
> return false;
>
> - if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)
> + if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
> return false;
>
> if (!ax45mp_iocp_sw_workaround())
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 83ed25e43553..4ed21a62158c 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -12,8 +12,8 @@
> #include <asm/vendorid_list.h>
>
> #ifdef CONFIG_ERRATA_ANDES
> -#define ERRATA_ANDESTECH_NO_IOCP 0
> -#define ERRATA_ANDESTECH_NUMBER 1
> +#define ERRATA_ANDES_NO_IOCP 0
> +#define ERRATA_ANDES_NUMBER 1
> #endif
>
> #ifdef CONFIG_ERRATA_SIFIVE
> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> index e55407ace0c3..2f2bb0c84f9a 100644
> --- a/arch/riscv/include/asm/vendorid_list.h
> +++ b/arch/riscv/include/asm/vendorid_list.h
> @@ -5,7 +5,7 @@
> #ifndef ASM_VENDOR_LIST_H
> #define ASM_VENDOR_LIST_H
>
> -#define ANDESTECH_VENDOR_ID 0x31e
> +#define ANDES_VENDOR_ID 0x31e
> #define SIFIVE_VENDOR_ID 0x489
> #define THEAD_VENDOR_ID 0x5b7
>
> diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
> index 319a1da0358b..0128b161bfda 100644
> --- a/arch/riscv/kernel/alternative.c
> +++ b/arch/riscv/kernel/alternative.c
> @@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
>
> switch (cpu_mfr_info->vendor_id) {
> #ifdef CONFIG_ERRATA_ANDES
> - case ANDESTECH_VENDOR_ID:
> + case ANDES_VENDOR_ID:
> cpu_mfr_info->patch_func = andes_errata_patch_func;
> break;
> #endif
> --
> 2.34.1
>
>
Powered by blists - more mailing lists