linux-kernel - Re: [PATCH 1/2] arm64: dts: qcom: sm6115: Add UART3

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Message-ID: <708925cc-abd6-4b90-b273-fbf9a34498d1@linaro.org>
Date:   Sat, 25 Nov 2023 14:48:41 +0000
From:   Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc:     Marijn Suijten <marijn.suijten@...ainline.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] arm64: dts: qcom: sm6115: Add UART3

On 25/11/2023 13:04, Konrad Dybcio wrote:
> Hook up UART3, usually used for communicating with a Bluetooth module.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm6115.dtsi | 30 ++++++++++++++++++++++++++++++
>   1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index 839c60351240..0d13d7bf6bd1 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -273,6 +273,25 @@ memory@...00000 {
>   		reg = <0 0x80000000 0 0>;
>   	};
>   
> +	qup_opp_table: opp-table-qup {
> +		compatible = "operating-points-v2";
> +
> +		opp-75000000 {
> +			opp-hz = /bits/ 64 <75000000>;
> +			required-opps = <&rpmpd_opp_low_svs>;
> +		};
> +
> +		opp-100000000 {
> +			opp-hz = /bits/ 64 <100000000>;
> +			required-opps = <&rpmpd_opp_svs>;
> +		};
> +
> +		opp-128000000 {
> +			opp-hz = /bits/ 64 <128000000>;
> +			required-opps = <&rpmpd_opp_nom>;
> +		};
> +	};
> +

It looked odd to me that the same opps as the FP4 were used but, this 
declaration is consistent with downstream.

>   	pmu {
>   		compatible = "arm,armv8-pmuv3";
>   		interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
> @@ -1208,6 +1227,17 @@ spi3: spi@...c000 {
>   				status = "disabled";
>   			};
>   
> +			uart3: serial@...c000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0x0 0x04a8c000 0x0 0x4000>;
> +				interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> +				clock-names = "se";
> +				power-domains = <&rpmpd SM6115_VDDCX>;
> +				operating-points-v2 = <&qup_opp_table>;
> +				status = "disabled";
> +			};
> +
>   			i2c4: i2c@...0000 {
>   				compatible = "qcom,geni-i2c";
>   				reg = <0x0 0x04a90000 0x0 0x4000>;
> 

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>