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Message-ID: <87fs0r84qw.fsf@nvidia.com>
Date: Mon, 27 Nov 2023 09:50:47 -0800
From: Rahul Rameshbabu <rrameshbabu@...dia.com>
To: Min Li <lnimi@...mail.com>
Cc: richardcochran@...il.com, lee@...nel.org,
linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
Min Li <min.li.xe@...esas.com>
Subject: Re: [PATCH net-next v5 1/1] ptp: clockmatrix: support 32-bit
address space
On Fri, 24 Nov, 2023 15:20:23 -0500 Min Li <lnimi@...mail.com> wrote:
> From: Min Li <min.li.xe@...esas.com>
>
> We used to assume 0x2010xxxx address. Now that
> we need to access 0x2011xxxx address, we need
> to support read/write the whole 32-bit address space.
>
> Signed-off-by: Min Li <min.li.xe@...esas.com>
> ---
> - Drop MAX_ABS_WRITE_PHASE_PICOSECONDS advised by Rahul
> - Apply SCSR_ADDR to scrach register in idtcm_load_firmware advised by Simon
> - Apply u32 to base in idtcm_output_enable advised by Simon
> - Correct sync_ctrl0/1 parameter position for idtcm_write advised by Simon
> - Restore adjphase function suggested by Rahul
>
> drivers/ptp/ptp_clockmatrix.c | 69 ++--
> drivers/ptp/ptp_clockmatrix.h | 32 +-
> include/linux/mfd/idt8a340_reg.h | 542 ++++++++++++++++---------------
> 3 files changed, 329 insertions(+), 314 deletions(-)
>
Looks good to me.
Reviewed-by: Rahul Rameshbabu <rrameshbabu@...dia.com>
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