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Message-ID: <cfea7192-4b29-46f9-a500-149121f493c8@intel.com>
Date: Mon, 27 Nov 2023 10:13:45 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Kai Huang <kai.huang@...el.com>, linux-kernel@...r.kernel.org,
kvm@...r.kernel.org
Cc: x86@...nel.org, kirill.shutemov@...ux.intel.com,
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pbonzini@...hat.com, rafael@...nel.org, david@...hat.com,
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isaku.yamahata@...el.com, ying.huang@...el.com, chao.gao@...el.com,
sathyanarayanan.kuppuswamy@...ux.intel.com, nik.borisov@...e.com,
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Subject: Re: [PATCH v15 17/23] x86/kexec: Flush cache of TDX private memory
On 11/9/23 03:55, Kai Huang wrote:
...
> --- a/arch/x86/kernel/reboot.c
> +++ b/arch/x86/kernel/reboot.c
> @@ -31,6 +31,7 @@
> #include <asm/realmode.h>
> #include <asm/x86_init.h>
> #include <asm/efi.h>
> +#include <asm/tdx.h>
>
> /*
> * Power off function, if any
> @@ -741,6 +742,20 @@ void native_machine_shutdown(void)
> local_irq_disable();
> stop_other_cpus();
> #endif
> + /*
> + * stop_other_cpus() has flushed all dirty cachelines of TDX
> + * private memory on remote cpus. Unlike SME, which does the
> + * cache flush on _this_ cpu in the relocate_kernel(), flush
> + * the cache for _this_ cpu here. This is because on the
> + * platforms with "partial write machine check" erratum the
> + * kernel needs to convert all TDX private pages back to normal
> + * before booting to the new kernel in kexec(), and the cache
> + * flush must be done before that. If the kernel took SME's way,
> + * it would have to muck with the relocate_kernel() assembly to
> + * do memory conversion.
> + */
> + if (platform_tdx_enabled())
> + native_wbinvd();
Why can't the TDX host code just set host_mem_enc_active=1?
Sure, you'll end up *using* the SME WBINVD support, but then you don't
have two different WBINVD call sites. You also don't have to mess with
a single line of assembly.
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