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Message-ID: <a1c651a3-31ed-4ee0-a7bf-a9f5e107bd33@linaro.org>
Date:   Mon, 27 Nov 2023 13:22:35 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Shengyang Chen <shengyang.chen@...rfivetech.com>,
        devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org
Cc:     andrzej.hajda@...el.com, neil.armstrong@...aro.org,
        rfoss@...nel.org, Laurent.pinchart@...asonboard.com,
        jonas@...boo.se, jernej.skrabec@...il.com,
        maarten.lankhorst@...ux.intel.com, mripard@...nel.org,
        tzimmermann@...e.de, airlied@...il.com, daniel@...ll.ch,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        conor+dt@...nel.org, p.zabel@...gutronix.de,
        tomi.valkeinen@...asonboard.com, r-ravikumar@...com,
        rdunlap@...radead.org, u.kleine-koenig@...gutronix.de,
        bbrezillon@...nel.org, changhuang.liang@...rfivetech.com,
        keith.zhao@...rfivetech.com, jack.zhu@...rfivetech.com,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 1/2] dt-bindings: display: bridge: cdns: Add properties
 to support StarFive JH7110 SoC

On 27/11/2023 12:34, Shengyang Chen wrote:
> From: Keith Zhao <keith.zhao@...rfivetech.com>
> 
> Add properties in CDNS DSI yaml file to match with
> CDNS DSI module in StarFive JH7110 SoC.
> 
> Signed-off-by: Keith Zhao <keith.zhao@...rfivetech.com>
> ---
>  .../bindings/display/bridge/cdns,dsi.yaml     | 38 ++++++++++++++++++-
>  1 file changed, 36 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
> index 23060324d16e..3f02ee383aad 100644
> --- a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.yaml
> @@ -17,6 +17,7 @@ properties:
>      enum:
>        - cdns,dsi
>        - ti,j721e-dsi
> +      - starfive,cdns-dsi

Keep alphabetical order.

>  
>    reg:
>      minItems: 1
> @@ -27,14 +28,20 @@ properties:
>            Register block for wrapper settings registers in case of TI J7 SoCs.
>  
>    clocks:
> +    minItems: 2
>      items:
>        - description: PSM clock, used by the IP
>        - description: sys clock, used by the IP
> +      - description: apb clock, used by the IP
> +      - description: txesc clock, used by the IP
>  
>    clock-names:
> +    minItems: 2
>      items:
>        - const: dsi_p_clk
>        - const: dsi_sys_clk
> +      - const: apb
> +      - const: txesc
>  
>    phys:
>      maxItems: 1
> @@ -46,10 +53,21 @@ properties:
>      maxItems: 1
>  
>    resets:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: dsi sys reset line
> +      - description: dsi dpi reset line
> +      - description: dsi apb reset line
> +      - description: dsi txesc reset line
> +      - description: dsi txbytehs reset line
>  
>    reset-names:
> -    const: dsi_p_rst
> +    items:
> +      - const: dsi_p_rst
> +      - const: dsi_dpi
> +      - const: dsi_apb
> +      - const: dsi_txesc
> +      - const: dsi_txbytehs
>  
>    ports:
>      $ref: /schemas/graph.yaml#/properties/ports
> @@ -90,6 +108,22 @@ allOf:
>          reg:
>            maxItems: 1
>  

You need to restrict other variants, because you just relaxed several
properties for everyone...


Best regards,
Krzysztof

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