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Message-ID: <ZWS6Hl2tZ0MPj+OL@shell.armlinux.org.uk>
Date: Mon, 27 Nov 2023 15:47:42 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Daniel Golle <daniel@...rotopia.org>
Cc: "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Chunfeng Yun <chunfeng.yun@...iatek.com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Felix Fietkau <nbd@....name>, John Crispin <john@...ozen.org>,
Sean Wang <sean.wang@...iatek.com>,
Mark Lee <Mark-MC.Lee@...iatek.com>,
Lorenzo Bianconi <lorenzo@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>,
Alexander Couzens <lynxis@...0.eu>,
Philipp Zabel <p.zabel@...gutronix.de>, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-phy@...ts.infradead.org
Subject: Re: [RFC PATCH 5/8] dt-bindings: net: pcs: add bindings for MediaTek
USXGMII PCS
On Thu, Nov 09, 2023 at 09:51:47PM +0000, Daniel Golle wrote:
> MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
> it in order to configure and monitor the Ethernet SerDes link in
> USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
> legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
> interface modes are also available.
I think this binding is based on the implementation than on hardware.
What I believe you have is this setup:
.---- LynxI PCS ----.
MAC ---+ +--- PEXTP --- world
`--- USXGMII PCS ---'
You are representing the PEXTP as a separate entity in DT, but then
you're representing the LynxI PCS and the USXGMII PCS as a single
block, which seems to be how you've decided to implement it.
Given that the LynxI PCS is already in use elsewhere in the Mediatek
range, I suggest that the LynxI PCS is one block of IP, and the USXGMII
PCS is a separate block of IP.
1) Would it not be better to model the two PCS seperately?
2) The addition of the SGMII reset needs more information - is this
controlling a reset for the LynxI block? If so, it should be part
of a LynxI PCS binding.
3) The PEXTP is presumably a separate block which can be shared between
several devices - for example, the LynxI, USXGMII, and probably SATA
and PCIe as well. From the 802.3's network model, the PEXTP is the
PMA/PMD.
From the point of view of 802.3's model, a network interface has
various layers such as the MAC, PCS and PMA/PMD, and sitting above
these layers is the management of the system. Rather than chasing
the data flow (which in a network device can be complex) wouldn't
it be better to continue with the 802.3 model as we are doing with
other devices, rather than trying to go with a new approach here?
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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