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Message-ID: <09c51c5301c54659828c5cce748d3762@EXMBX066.cuchost.com>
Date: Tue, 28 Nov 2023 03:23:29 +0000
From: JeeHeng Sia <jeeheng.sia@...rfivetech.com>
To: Krzysztof Kozlowski <krzk@...nel.org>,
"paul.walmsley@...ive.com" <paul.walmsley@...ive.com>,
"palmer@...belt.com" <palmer@...belt.com>,
"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
"conor@...nel.org" <conor@...nel.org>,
"kernel@...il.dk" <kernel@...il.dk>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"emil.renner.berthing@...onical.com"
<emil.renner.berthing@...onical.com>
CC: "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Leyfoon Tan <leyfoon.tan@...rfivetech.com>
Subject: RE: [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100
device tree
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@...nel.org>
> Sent: Monday, November 27, 2023 4:51 PM
> To: JeeHeng Sia <jeeheng.sia@...rfivetech.com>; paul.walmsley@...ive.com; palmer@...belt.com; aou@...s.berkeley.edu;
> conor@...nel.org; kernel@...il.dk; robh+dt@...nel.org; emil.renner.berthing@...onical.com
> Cc: linux-riscv@...ts.infradead.org; linux-kernel@...r.kernel.org; Leyfoon Tan <leyfoon.tan@...rfivetech.com>
> Subject: Re: [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree
>
> On 27/11/2023 02:36, Sia Jee Heng wrote:
> > Add initial device tree for the StarFive JH8100 RISC-V SoC
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/Makefile | 1 +
> > arch/riscv/boot/dts/starfive/jh8100-evb.dts | 42 +++
> > arch/riscv/boot/dts/starfive/jh8100.dtsi | 365 ++++++++++++++++++++
> > 3 files changed, 408 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts
> > create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> > index 0141504c0f5c..fbb0dc619102 100644
> > --- a/arch/riscv/boot/dts/starfive/Makefile
> > +++ b/arch/riscv/boot/dts/starfive/Makefile
> > @@ -10,3 +10,4 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
> >
> > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> > dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> > +dtb-$(CONFIG_ARCH_STARFIVE) += jh8100-evb.dtb
> > diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/dts/starfive/jh8100-evb.dts
> > new file mode 100644
> > index 000000000000..67c4964a8773
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts
> > @@ -0,0 +1,42 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd.
> > + */
> > +
> > +#include "jh8100.dtsi"
> > +
> > +/ {
> > + model = "StarFive JH8100 EVB";
> > + compatible = "starfive,jh8100-evb", "starfive,jh8100";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + cpus {
> > + timebase-frequency = <4000000>;
>
> This was fixed recently on the mailing lists.
The timebase-frequency on StarFive JH8100 SoC is set by an internal clk divider, will move the property to jh8100.dtsi. Thanks.
>
>
> > +
> > + };
> > +
> > + memory {
> > + device_type = "memory";
> > + reg = <0x0 0x40000000 0x2 0x00000000>; /* 8GB */
> > + };
> > +
> > + soc {
> > + clk_uart: clk_uart {
>
> Undercores are not allowed in node names. Use hyphen.
Noted.
>
> Also, boards must not add nodes to the soc. This is board, not SoC DTS.
Noted. Will move it to dtsi.
>
> ...
>
> > +
> > + uart6: serial@...e0000 {
> > + compatible = "starfive,jh8100-uart";
> > + reg = <0x0 0x127e0000 0x0 0x10000>;
> > + clock-names = "uart_clk", "pclk";
> > + interrupts = <73>;
> > + status = "disabled";
> > + };
> > +
>
> Stray blank line. In other places as well.
Noted.
>
> > + };
> > +};
>
> Best regards,
> Krzysztof
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