linux-kernel - Re: [PATCH v2 1/2] arm64: dts: ti: k3-am62a-main: Add sdhci0 instance

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <6eab794f-a5cf-455a-9b49-bc73259bd58e@ti.com>
Date:   Tue, 28 Nov 2023 13:58:33 -0600
From:   Judith Mendez <jm@...com>
To:     Nitin Yadav <n-yadav@...com>, <nm@...com>, <vigneshr@...com>,
        <kristo@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] arm64: dts: ti: k3-am62a-main: Add sdhci0 instance

Hi Nitin,

On 11/27/23 10:39 PM, Nitin Yadav wrote:
> 
> 
> On 11/28/2023 3:11 AM, Judith Mendez wrote:
>> On 10/30/23 1:31 AM, Nitin Yadav wrote:
>>> Add sdhci0 DT node in k3-am62a-main for eMMC support. Droping
>>> ITAP values as they are NA in datasheet[0] for lower speed modes.
>>>
>>> [0]https://www.ti.com/lit/gpn/am62a3 Table: 7-79 (Page No. 179)
>>>
>>
>> Minor comment below. All else looks good to me.
>>
>> Reviewed by: Judith Mendez <jm@...com>
>>
>>> Signed-off-by: Nitin Yadav <n-yadav@...com>
>>> ---
>>>    arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 19 +++++++++++++++++++
>>>    1 file changed, 19 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> index de36abb243f1..89b8b7d302cd 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
>>> @@ -488,6 +488,25 @@ main_gpio1: gpio@...000 {
>>>            status = "disabled";
>>>        };
>>>    +    sdhci0: mmc@...0000 {
>>> +        compatible = "ti,am62-sdhci";
>>> +        reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
>>> +        interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>>> +        power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
>>> +        clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
>>> +        clock-names = "clk_ahb", "clk_xin";
>>> +        assigned-clocks = <&k3_clks 57 6>;
>>> +        assigned-clock-parents = <&k3_clks 57 8>;
>>> +        mmc-hs200-1_8v;
>>> +        ti,trm-icp = <0x2>;
>>> +        ti,otap-del-sel-legacy = <0x0>;
>>> +        ti,otap-del-sel-mmc-hs = <0x0>;
>>> +        ti,otap-del-sel-hs200 = <0x6>;
>>
>> I am wondering why DDR52 speed mode was not added?
> plz refer datasheet. No mention of DDR52 in this revised addition.
I believe it is mentioned in the RIOT, not datasheet.

>>
>>> +        bus-width = <8>;
>>> +        ti,clkbuf-sel = <0x7>;
>>> +        status = "disabled";
>>> +    };
>>> +
>>>        sdhci1: mmc@...0000 {
>>>            compatible = "ti,am62-sdhci";
>>>            reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
>>
>> ~ Judith