linux-kernel - Re: [PATCH v2 05/15] clk: qcom: gpucc-sm6375: Unregister critical clocks

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 29 Nov 2023 21:10:47 +0000
From:   Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To:     Konrad Dybcio <konrad.dybcio@...aro.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Andy Gross <agross@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc:     Marijn Suijten <marijn.suijten@...ainline.org>,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 05/15] clk: qcom: gpucc-sm6375: Unregister critical
 clocks

On 29/11/2023 18:59, Konrad Dybcio wrote:
> Some clocks need to be always-on, but we don't really do anything
> with them, other than calling enable() once and telling Linux they're
> enabled.
> 
> Unregister them to save a couple of bytes and, perhaps more
> importantly, allow for runtime suspend of the clock controller device,
> as CLK_IS_CRITICAL prevents the latter.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
> ---
>   drivers/clk/qcom/gpucc-sm6375.c | 33 +++------------------------------
>   1 file changed, 3 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c
> index da24276a018e..6d85936dd441 100644
> --- a/drivers/clk/qcom/gpucc-sm6375.c
> +++ b/drivers/clk/qcom/gpucc-sm6375.c
> @@ -183,20 +183,6 @@ static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = {
>   	},
>   };
>   
> -static struct clk_branch gpucc_ahb_clk = {
> -	.halt_reg = 0x1078,
> -	.halt_check = BRANCH_HALT_DELAY,
> -	.clkr = {
> -		.enable_reg = 0x1078,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "gpucc_ahb_clk",
> -			.flags = CLK_IS_CRITICAL,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>   static struct clk_branch gpucc_cx_gfx3d_clk = {
>   	.halt_reg = 0x10a4,
>   	.halt_check = BRANCH_HALT_DELAY,
> @@ -294,20 +280,6 @@ static struct clk_branch gpucc_cxo_clk = {
>   	},
>   };
>   
> -static struct clk_branch gpucc_gx_cxo_clk = {
> -	.halt_reg = 0x1060,
> -	.halt_check = BRANCH_HALT_DELAY,
> -	.clkr = {
> -		.enable_reg = 0x1060,
> -		.enable_mask = BIT(0),
> -		.hw.init = &(struct clk_init_data){
> -			.name = "gpucc_gx_cxo_clk",
> -			.flags = CLK_IS_CRITICAL,
> -			.ops = &clk_branch2_ops,
> -		},
> -	},
> -};
> -
>   static struct clk_branch gpucc_gx_gfx3d_clk = {
>   	.halt_reg = 0x1054,
>   	.halt_check = BRANCH_HALT_DELAY,
> @@ -381,7 +353,6 @@ static struct gdsc gpu_gx_gdsc = {
>   };
>   
>   static struct clk_regmap *gpucc_sm6375_clocks[] = {
> -	[GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr,
>   	[GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr,
>   	[GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr,
>   	[GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr,
> @@ -389,7 +360,6 @@ static struct clk_regmap *gpucc_sm6375_clocks[] = {
>   	[GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr,
>   	[GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr,
>   	[GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr,
> -	[GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr,
>   	[GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr,
>   	[GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr,
>   	[GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr,
> @@ -455,6 +425,9 @@ static int gpucc_sm6375_probe(struct platform_device *pdev)
>   	clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
>   	clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
>   
> +	qcom_branch_set_clk_en(regmap, 0x1078); /* GPUCC_AHB_CLK */
> +	qcom_branch_set_clk_en(regmap, 0x1060); /* GPUCC_GX_CXO_CLK */
> +
>   	ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
>   	pm_runtime_put(&pdev->dev);
>   
> 

I think this makes sense for a CLK_IS_CRITICAL clock - why bother 
enumerating halt regs/semantics we never use..

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>