linux-kernel - Re: [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string

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Message-ID: <ZWbdmRFfhMcQY_zS@APC323>
Date:   Wed, 29 Nov 2023 14:43:37 +0800
From:   Yu-Chien Peter Lin <peterlin@...estech.com>
To:     "Lad, Prabhakar" <prabhakar.csengg@...il.com>
CC:     <acme@...nel.org>, <adrian.hunter@...el.com>,
        <ajones@...tanamicro.com>, <alexander.shishkin@...ux.intel.com>,
        <andre.przywara@....com>, <anup@...infault.org>,
        <aou@...s.berkeley.edu>, <atishp@...shpatra.org>,
        <conor+dt@...nel.org>, <conor.dooley@...rochip.com>,
        <conor@...nel.org>, <devicetree@...r.kernel.org>,
        <dminus@...estech.com>, <evan@...osinc.com>,
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Subject: Re: [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt
 controller compatible string

Hi Prabhakar,

On Fri, Nov 24, 2023 at 03:03:51PM +0000, Lad, Prabhakar wrote:
> On Wed, Nov 22, 2023 at 12:18 PM Yu Chien Peter Lin
> <peterlin@...estech.com> wrote:
> >
> > Add "andestech,cpu-intc" compatible string to indicate that
> > Andes specific local interrupt is supported on the core,
> > e.g. AX45MP cores have 3 types of non-standard local interrupt
> > can be handled in supervisor mode:
> >
> > - Slave port ECC error interrupt
> > - Bus write transaction error interrupt
> > - Performance monitor overflow interrupt
> >
> > These interrupts are enabled/disabled via a custom register
> > SLIE instead of the standard interrupt enable register SIE.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> > ---
> > Changes v1 -> v2:
> >   - New patch
> > Changes v2 -> v3:
> >   - Updated commit message
> >   - Fixed possible compatibles for Andes INTC
> > Changes v3 -> v4:
> >   - Add const entry instead of enum (Suggested by Conor)
> > ---
> >  Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index f392e367d673..50307554478f 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -100,7 +100,11 @@ properties:
> >          const: 1
> >
> >        compatible:
> > -        const: riscv,cpu-intc
> > +        oneOf:
> > +          - items:
> > +              - const: andestech,cpu-intc
> given that the first patch renames andestech -> andes, do you want to
> follow the same here?

Thanks for pointing this out.
We would like to use "andestech" for compatible string.

Documentation/devicetree/bindings/vendor-prefixes.yaml
118:  "^andestech,.*":
119-    description: Andes Technology Corporation

> > +              - const: riscv,cpu-intc
> > +          - const: riscv,cpu-intc
> >
> >        interrupt-controller: true
> >
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Thanks for the review!

Best regards,
Peter Lin

> Cheers,
> Prabhakar
> 
> > --
> > 2.34.1
> >
> >