linux-kernel - Re: [PATCH V2 3/5] arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts

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Message-ID: <c6e05a10-88cc-409c-afc0-37166b763eaa@linaro.org>
Date:   Wed, 29 Nov 2023 13:54:49 +0100
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Sibi Sankar <quic_sibis@...cinc.com>, andersson@...nel.org,
        robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        catalin.marinas@....com, ulf.hansson@...aro.org
Cc:     agross@...nel.org, conor+dt@...nel.org, ayan.kumar.halder@....com,
        j@...nau.net, dmitry.baryshkov@...aro.org, nfraprado@...labora.com,
        m.szyprowski@...sung.com, u-kumar1@...com, peng.fan@....com,
        lpieralisi@...nel.org, quic_rjendra@...cinc.com,
        abel.vesa@...aro.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, quic_tsoni@...cinc.com,
        neil.armstrong@...aro.org
Subject: Re: [PATCH V2 3/5] arm64: dts: qcom: Add base X1E80100 dtsi and the
 QCP dts

On 29.11.2023 10:25, Sibi Sankar wrote:
> 
> 
> On 11/18/23 06:36, Konrad Dybcio wrote:
>> On 17.11.2023 12:39, Sibi Sankar wrote:
>>> From: Rajendra Nayak <quic_rjendra@...cinc.com>
>>>
>>> Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for
>>> X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers,
>>> geni UART, interrupt controller, TLMM, reserved memory, interconnects,
>>> SMMU and LLCC nodes.
>>>
>>> Co-developed-by: Abel Vesa <abel.vesa@...aro.org>
>>> Signed-off-by: Abel Vesa <abel.vesa@...aro.org>
>>> Signed-off-by: Rajendra Nayak <quic_rjendra@...cinc.com>
>>> Co-developed-by: Sibi Sankar <quic_sibis@...cinc.com>
>>> Signed-off-by: Sibi Sankar <quic_sibis@...cinc.com>
>>> ---
[...]


>>> +        idle-states {
>>> +            entry-method = "psci";
>>> +
>>> +            CLUSTER_C4: cpu-sleep-0 {
>>> +                compatible = "arm,idle-state";
>>> +                idle-state-name = "ret";
>>> +                arm,psci-suspend-param = <0x00000004>;
>> These suspend parameters look funky.. is this just a PSCI sleep
>> implementation that strays far away from Arm's suggested guidelines?
> 
> not really! it's just that 30th bit is set according to spec i.e
> it's marked as a retention state.
So, is there no state where the cores actually power down? Or is it
not described yet?

FWIW by "power down" I mean it in the sense that Arm DEN0022D does,
so "In this state the core is powered off. Software on the device
needs to save all core state, so that it can be preserved over
the powerdown."

> 
>>
>> [...]
>>
>>
>>> +        CPU_PD11: power-domain-cpu11 {
>>> +            #power-domain-cells = <0>;
>>> +            power-domains = <&CLUSTER_PD>;
>>> +        };
>>> +
>>> +        CLUSTER_PD: power-domain-cpu-cluster {
>>> +            #power-domain-cells = <0>;
>>> +            domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>;
>>> +        };
>> So, can the 3 clusters not shut down their L2 and PLLs (if separate?)
>> on their own?
> 
> on CL5 the clusters are expected to shutdown their l2 and PLL on their
> own.
Then I think this won't happen with this description

every cpu has a genpd tree like this:

cpu_n
 |_CPU_PDn
    |_CLUSTER_PD

and CLUSTER_PD has two idle states: CLUSTER_CL4 and CLUSTER_CL5

which IIUC means that neither cluster idle state will be reached
unless all children of CLUSTER_PD (so, all CPUs) go down that low

This is "fine" on e.g. sc8280 where both CPU clusters are part of
the same Arm DynamIQ cluster (which is considered one cluster as
far as MPIDR_EL1 goes) (though perhaps that's misleading and with
the qcom plumbing they perhaps could actually be collapsed separately)

Konrad