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Message-ID: <ac934dc1-0239-47c6-b28d-d4cd690f54c1@starfivetech.com>
Date: Thu, 30 Nov 2023 15:33:56 +0800
From: William Qiu <william.qiu@...rfivetech.com>
To: Conor Dooley <conor@...nel.org>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-pwm@...r.kernel.org>,
"Emil Renner Berthing" <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Uwe Kleine-König <u.kleine-koenig@...gutronix.de>,
Hal Feng <hal.feng@...rfivetech.com>,
"Paul Walmsley" <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Subject: Re: [PATCH v8 1/4] dt-bindings: pwm: Add bindings for OpenCores PWM
Controller
On 2023/11/29 22:33, Conor Dooley wrote:
> On Wed, Nov 29, 2023 at 05:27:29PM +0800, William Qiu wrote:
>> Add bindings for OpenCores PWM Controller.
>>
>> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
>> ---
>> .../bindings/pwm/opencores,pwm.yaml | 56 +++++++++++++++++++
>> 1 file changed, 56 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>> new file mode 100644
>> index 000000000000..133f2cd417f0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>> @@ -0,0 +1,56 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: OpenCores PWM controller
>> +
>> +maintainers:
>> + - William Qiu <william.qiu@...rfivetech.com>
>> +
>> +description:
>> + OpenCores PTC ip core contains a PWM controller. When operating in PWM mode,
>
> nit: "The OpenCores PTC IP core"
>
Will update.
>> + the PTC core generates binary signal with user-programmable low and high
>> + periods. All PTC counters and registers are 32-bit.
>> +
>> +allOf:
>> + - $ref: pwm.yaml#
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - items:
>> + - enum:
>> + - starfive,jh7100-pwm
>> + - starfive,jh7110-pwm
>> + - const: opencores,pwm-v1
>
> properties:
> compatible:
> items:
> - enum:
> - starfive,jh7100-pwm
> - starfive,jh7110-pwm
> - const: opencores,pwm-v1
>
> Please use this form here instead.
>
> Otherwise, this looks good to me now.
>
I see. I'll update it.
Thanks for spending time to review this patchset.
Best Regards,
William
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + resets:
>> + maxItems: 1
>> +
>> + "#pwm-cells":
>> + const: 3
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + pwm@...90000 {
>> + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
>> + reg = <0x12490000 0x10000>;
>> + clocks = <&clkgen 181>;
>> + resets = <&rstgen 109>;
>> + #pwm-cells = <3>;
>> + };
>> --
>> 2.34.1
>>
>>
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