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Message-ID: <CAK9=C2UWwHVCvgXG0kNLt86JTk7P6p-EdPLS3F8Z5qnSpCPLkg@mail.gmail.com>
Date: Thu, 30 Nov 2023 17:54:43 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Conor Dooley <conor@...nel.org>
Cc: Inochi Amaoto <inochiama@...look.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Chen Wang <unicorn_wang@...look.com>,
Anup Patel <anup@...infault.org>,
Samuel Holland <samuel.holland@...ive.com>,
Guo Ren <guoren@...nel.org>,
Jisheng Zhang <jszhang@...nel.org>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v4 1/2] dt-bindings: timer: thead,c900-aclint-mtimer:
separate mtime and mtimecmp regs
On Thu, Nov 30, 2023 at 5:40 PM Conor Dooley <conor@...nel.org> wrote:
>
> On Thu, Nov 30, 2023 at 05:18:15PM +0530, Anup Patel wrote:
> > On Thu, Nov 30, 2023 at 5:15 PM Conor Dooley <conor@...nel.org> wrote:
>
> > > > and add separate "riscv" prefixed DT binding for RISC-V mtimer.
> > >
> > > Do you know of any users for a "riscv,mtimer" binding that are not
> > > covered by existing bindings for the clint?
> >
> > Ventana Veyron-v1 implements a mtimer per-cluster (or chiplet)
> > which is compatible to "riscv,mtimer" (i.e. we have both mtime
> > and mtimecmp MMIO registers).
>
> Okay, thanks. I guess iff veyron-v1 DT support shows up (or other
> similar devices) we can go ahead with a "riscv,mtimer" binding then.
> I had thought that you guys were going to be using ACPI though, so
> I guess the "other similar devices" applies.
We use ACPI from EDK2 onwards in our boot-flow. The booting
stages prior to EDK2 (such as OpenSBI) use DT. In fact, EDK2
also uses information in DT to populate static parts of the ACPI
table.
Regards,
Anup
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