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Message-ID: <CAJM55Z_EPMuCbX-_8ABKwT27xdtDX7X2y_nv+o4knVL0DoK2xQ@mail.gmail.com>
Date: Thu, 30 Nov 2023 16:04:35 +0100
From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
To: Conor Dooley <conor@...nel.org>,
Emil Renner Berthing <emil.renner.berthing@...onical.com>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
Subject: Re: [PATCH v1 0/8] Add JH7100 errata and update device tree
Conor Dooley wrote:
> On Mon, Nov 27, 2023 at 12:27:38AM +0100, Emil Renner Berthing wrote:
> > Now that the driver for the SiFive cache controller supports manual
> > flushing as non-standard cache operations[1] we can add an errata option
> > for the StarFive JH7100 SoC and update the device tree with the cache
> > controller, dedicated DMA pool and add MMC nodes for the SD-card and
> > wifi.
> >
> > This series needs the following commit in [1] to work properly:
> >
> > 0d5701dc9cd6 ("soc: sifive: ccache: Add StarFive JH7100 support")
> >
> > [1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=riscv-soc-for-next
>
> This stuff all seems fine to me. I'd like Palmer to take the first
> patch, or I suppose I could take it alongside the cache driver changes
> with an Ack.
Thanks, makes sense. In addition to the missing Signed-off-by I also forgot to
update the commit message for patch 4/8, so let me send a v2.
/Emil
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