linux-kernel - [PATCH v1] riscv: dts: starfive: move timebase-frequency to .dtsi

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20231130-bobbing-valid-b97f26fe8edc@spud>
Date:   Thu, 30 Nov 2023 16:11:28 +0000
From:   Conor Dooley <conor@...nel.org>
To:     linux-riscv@...ts.infradead.org
Cc:     conor@...nel.org, Conor Dooley <conor.dooley@...rochip.com>,
        Emil Renner Berthing <kernel@...il.dk>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Walker Chen <walker.chen@...rfivetech.com>,
        JeeHeng Sia <jeeheng.sia@...rfivetech.com>,
        Leyfoon Tan <leyfoon.tan@...rfivetech.com>
Subject: [PATCH v1] riscv: dts: starfive: move timebase-frequency to .dtsi

From: Conor Dooley <conor.dooley@...rochip.com>

Properties fixed by the SoC should be defined in the $soc.dtsi, and the
timebase-frequency is not sourced directly from an off-chip oscillator.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
I actually have no idea whether this is true or not, I asked on the
jh8100 series but only got an answer for that SoC and not the existing
ones. I'm hoping that a patch envokes more of a reaction!

CC: Emil Renner Berthing <kernel@...il.dk>
CC: Conor Dooley <conor@...nel.org>
CC: Rob Herring <robh+dt@...nel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
CC: Paul Walmsley <paul.walmsley@...ive.com>
CC: Palmer Dabbelt <palmer@...belt.com>
CC: linux-riscv@...ts.infradead.org
CC: devicetree@...r.kernel.org
CC: linux-kernel@...r.kernel.org
CC: Walker Chen <walker.chen@...rfivetech.com>
CC: JeeHeng Sia <jeeheng.sia@...rfivetech.com>
CC: Leyfoon Tan <leyfoon.tan@...rfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7100-common.dtsi               | 4 ----
 arch/riscv/boot/dts/starfive/jh7100.dtsi                      | 1 +
 .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ----
 arch/riscv/boot/dts/starfive/jh7110.dtsi                      | 1 +
 4 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index b93ce351a90f..214f27083d7b 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -19,10 +19,6 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	cpus {
-		timebase-frequency = <6250000>;
-	};
-
 	memory@...00000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0x2 0x0>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index e68cafe7545f..c50b32424721 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -16,6 +16,7 @@ / {
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		timebase-frequency = <6250000>;
 
 		U74_0: cpu@0 {
 			compatible = "sifive,u74-mc", "riscv";
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index b89e9791efa7..7873c7ffde4d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -26,10 +26,6 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	cpus {
-		timebase-frequency = <4000000>;
-	};
-
 	memory@...00000 {
 		device_type = "memory";
 		reg = <0x0 0x40000000 0x1 0x0>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 45213cdf50dc..ee7d4bb1f537 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -18,6 +18,7 @@ / {
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		timebase-frequency = <4000000>;
 
 		S7_0: cpu@0 {
 			compatible = "sifive,s7", "riscv";
-- 
2.39.2