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Message-ID: <CABCJKufwox6C5BprNF=rDUxfV532OcawqZBsv5hFejJgrfZ+FA@mail.gmail.com>
Date:   Fri, 1 Dec 2023 09:40:55 -0800
From:   Sami Tolvanen <samitolvanen@...gle.com>
To:     Samuel Holland <samuel.holland@...ive.com>
Cc:     Palmer Dabbelt <palmer@...belt.com>,
        linux-riscv@...ts.infradead.org, Albert Ou <aou@...s.berkeley.edu>,
        Andy Chiu <andy.chiu@...ive.com>,
        Clément Léger <cleger@...osinc.com>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Greentime Hu <greentime.hu@...ive.com>,
        Guo Ren <guoren@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
        Masahiro Yamada <masahiroy@...nel.org>,
        Nam Cao <namcaov@...il.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: Fix SMP when shadow call stacks are enabled

Hi Samuel,

On Tue, Nov 21, 2023 at 1:20 PM Samuel Holland
<samuel.holland@...ive.com> wrote:
>
> This fixes two bugs in SCS initialization for secondary CPUs. First,
> the SCS was not initialized at all in the spinwait boot path. Second,
> the code for the SBI HSM path attempted to initialize the SCS before
> enabling the MMU. However, that involves dereferencing the thread
> pointer, which requires the MMU to be enabled.
>
> Fix both issues by setting up the SCS in the common secondary entry
> path, after enabling the MMU.

Thanks for the patch! Looks like my qemu setup doesn't hit this issue,
but nevertheless, the fix looks good to me.

Reviewed-by: Sami Tolvanen <samitolvanen@...gle.com>

Sami

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