lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <84c102fa-e3f4-4454-82c9-95eea7eeb941@lunn.ch>
Date:   Fri, 1 Dec 2023 23:15:24 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
        edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
        quentin.schulz@...obroma-systems.com,
        Heiko Stuebner <heiko.stuebner@...rry.de>
Subject: Re: [PATCH] net: mdio: enable optional clock when registering a phy
 from devicetree

On Fri, Dec 01, 2023 at 03:24:53PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@...rry.de>
> 
> The ethernet-phy binding (now) specifys that phys can declare a clock
> supply. Phy driver itself will handle this when probing the phy-driver.
> 
> But there is a gap when trying to detect phys, because the mdio-bus needs
> to talk to the phy to get its phy-id. Using actual phy-ids in the dt like
>        compatible = "ethernet-phy-id0022.1640",
>                     "ethernet-phy-ieee802.3-c22";
> of course circumvents this, but in turn hard-codes the phy.
> 
> With boards often having multiple phy options and the mdio-bus being able
> to actually probe devices, this feels like a step back.
> 
> So check for the existence of a phy-clock per the -dtbinding in the
> of_mdiobus_register_phy() and enable the clock around the
> fwnode_mdiobus_register_phy() call which tries to determine the phy-id.

Why handle this separately to the reset GPIO and the reset controller?

    Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ