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Message-ID: <20231130-encoder-fixup-v1-0-585c54cd046e@quicinc.com> Date: Thu, 30 Nov 2023 17:30:32 -0800 From: Jessica Zhang <quic_jesszhan@...cinc.com> To: Rob Clark <robdclark@...il.com>, Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, Sean Paul <sean@...rly.run>, Marijn Suijten <marijn.suijten@...ainline.org>, David Airlie <airlied@...il.com>, "Daniel Vetter" <daniel@...ll.ch> CC: <quic_abhinavk@...cinc.com>, <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>, <freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>, Jessica Zhang <quic_jesszhan@...cinc.com> Subject: [PATCH 0/2] drm/msm/dpu: INTF CRC configuration cleanups and fix This series drops the frame_count and enable parameters (as they're always set to the same value). It also sets input_sel=0x1 for INTF. Signed-off-by: Jessica Zhang <quic_jesszhan@...cinc.com> --- Jessica Zhang (2): drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr() drm/msm/dpu: Set input_sel bit for INTF drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 11 +++++------ 8 files changed, 26 insertions(+), 30 deletions(-) --- base-commit: 4047f50eb64d980fcd581a19bbe6164dab25ebc7 change-id: 20231122-encoder-fixup-61c190b16085 Best regards, -- Jessica Zhang <quic_jesszhan@...cinc.com>
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