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Message-Id: <20231202092041.14084-1-yan.y.zhao@intel.com>
Date: Sat, 2 Dec 2023 17:20:41 +0800
From: Yan Zhao <yan.y.zhao@...el.com>
To: iommu@...ts.linux.dev, kvm@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: alex.williamson@...hat.com, jgg@...dia.com, pbonzini@...hat.com,
seanjc@...gle.com, joro@...tes.org, will@...nel.org,
robin.murphy@....com, kevin.tian@...el.com,
baolu.lu@...ux.intel.com, dwmw2@...radead.org, yi.l.liu@...el.com,
Yan Zhao <yan.y.zhao@...el.com>
Subject: [RFC PATCH 11/42] iommu: Add new domain op cache_invalidate_kvm
On KVM invalidates mappings that are shared to IOMMU stage 2 paging
structures, IOMMU driver needs to invalidate hardware TLBs accordingly.
The new op cache_invalidate_kvm is called from IOMMUFD to invalidate
hardware TLBs upon receiving invalidation notifications from KVM.
Signed-off-by: Yan Zhao <yan.y.zhao@...el.com>
---
include/linux/iommu.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 0ce23ee399d35..0b056d5a6b3a3 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -636,6 +636,9 @@ struct iommu_ops {
* forward a driver specific error code to user space.
* Both the driver data structure and the error code
* must be defined in include/uapi/linux/iommufd.h
+ * @cache_invalidate_kvm: Synchronously flush hardware TLBs for KVM managed
+ * stage 2 IO page tables.
+ * The @domain must be IOMMU_DOMAIN_KVM.
* @iova_to_phys: translate iova to physical address
* @enforce_cache_coherency: Prevent any kind of DMA from bypassing IOMMU_CACHE,
* including no-snoop TLPs on PCIe or other platform
@@ -665,6 +668,8 @@ struct iommu_domain_ops {
int (*cache_invalidate_user)(struct iommu_domain *domain,
struct iommu_user_data_array *array,
u32 *error_code);
+ void (*cache_invalidate_kvm)(struct iommu_domain *domain,
+ unsigned long iova, unsigned long size);
phys_addr_t (*iova_to_phys)(struct iommu_domain *domain,
dma_addr_t iova);
--
2.17.1
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