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Message-ID: <IA1PR20MB49539388196F08BBA969B522BB80A@IA1PR20MB4953.namprd20.prod.outlook.com>
Date:   Sat,  2 Dec 2023 08:22:10 +0800
From:   Inochi Amaoto <inochiama@...look.com>
To:     Conor Dooley <conor@...nel.org>
Cc:     Inochi Amaoto <inochiama@...look.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Chao Wei <chao.wei@...hgo.com>,
        Chen Wang <unicorn_wang@...look.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Anup Patel <anup@...infault.org>,
        Conor Dooley <conor.dooley@...rochip.com>,
        Jisheng Zhang <jszhang@...nel.org>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v4 0/7] Add Huashan Pi board support

>
>On Fri, Dec 01, 2023 at 04:31:38PM +0800, Inochi Amaoto wrote:
>>>
>>> On Fri, Dec 01, 2023 at 09:02:59AM +0800, Inochi Amaoto wrote:
>>>>>
>>>>> On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
>>>>>>>
>>>>>>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
>>>>>>>> Huashan Pi board is an embedded development platform based on the
>>>>>>>> CV1812H chip. Add minimal device tree files for this board.
>>>>>>>> Currently, it can boot to a basic shell.
>>>>>>>>
>>>>>>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>>>>>>>>
>>>>>>>> Link: https://en.sophgo.com/product/introduce/huashan.html
>>>>>>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
>>>>>>>> Link: https://lore.kernel.org/linux-riscv/20231006121449.721-1-jszhang@kernel.org/
>>>>>>>>
>>>>>>>> [...]
>>>>>>>
>>>>>>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
>>>>>>> expected.
>>>>>>>
>>>>>>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>>>>>>>      https://git.kernel.org/conor/c/21a34e63afcc
>>>>>>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
>>>>>>>      https://git.kernel.org/conor/c/06ea2a1968a9
>>>>>>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>>>>>>>      https://git.kernel.org/conor/c/d7b92027834e
>>>>>>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
>>>>>>>      https://git.kernel.org/conor/c/5b5dce3951b2
>>>>>>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
>>>>>>>      https://git.kernel.org/conor/c/dd791b45c866
>>>>>>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
>>>>>>>      https://git.kernel.org/conor/c/681ec684a741
>>>>>>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
>>>>>>>      https://git.kernel.org/conor/c/2c36b0cfb408
>>>
>>>>>> Thanks for the confirmation. But I suggest to revert these patches.
>>>>>> Several days ago, Sophgo informed me that CV1810 series will be
>>>>>> renamed. And the Huashan Pi will switch to the chip with new name.
>>>>>> To avoid unnecessary conflict, please drop these patch and I will
>>>>>> prepare a new patch once the renamed chip is launched.
>>>>>
>>>>> This is a board that exists, that you (and possibly others) have, right?
>>>>>
>>>>
>>>> Yes, of course.
>>>
>>> I dunno then. It sounds from your message that this is purely a rebrand
>>> of the SoCs,
>>
>> IIRC, it is.
>> FYI, Chen and Chao. Maybe you know something more.
>>
>>> so since people already have these boards, I'd rather not.
>>> We should be able to support both since it's just a naming change,
>>> right?
>>
>> I agree with this. If the above is true, we can just reuse the exists code
>> with a different compatible name, right?
>
>I think so? I'm not sure what the precedent really is for pure
>rebrandings of an SoC.
>I say for now, assume we can do that, and we can discuss it with Rob and
>Krzysztof when the time comes if there is no difference between the SoCs
>and boards.
>

OK, now let's reserve these code and discuss when the board with
those SoCs come. Thanks for your explanation.

>Cheers,
>Conor.
>
>

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