| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20231204230845.GH981228@pengutronix.de>
Date: Tue, 5 Dec 2023 00:08:45 +0100
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: Kory Maincent <kory.maincent@...tlin.com>
Cc: "David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Jonathan Corbet <corbet@....net>,
Luis Chamberlain <mcgrof@...nel.org>,
Russ Weight <russ.weight@...ux.dev>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org, devicetree@...r.kernel.org,
Dent Project <dentproject@...uxfoundation.org>
Subject: Re: [PATCH net-next v2 7/8] dt-bindings: net: pse-pd: Add bindings
for PD692x0 PSE controller
On Fri, Dec 01, 2023 at 06:10:29PM +0100, Kory Maincent wrote:
> Add the PD692x0 I2C Power Sourcing Equipment controller device tree
> bindings documentation.
>
> Sponsored-by: Dent Project <dentproject@...uxfoundation.org>
> Signed-off-by: Kory Maincent <kory.maincent@...tlin.com>
> ---
>
> Changes in v2:
> - Enhance ports-matrix description.
> - Replace additionalProperties by unevaluatedProperties.
> - Drop i2c suffix.
> ---
> .../bindings/net/pse-pd/microchip,pd692x0.yaml | 77 ++++++++++++++++++++++
> MAINTAINERS | 6 ++
> 2 files changed, 83 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml
> new file mode 100644
> index 000000000000..3ce81cf99215
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/pse-pd/microchip,pd692x0.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PD692x0 Power Sourcing Equipment controller
> +
> +maintainers:
> + - Kory Maincent <kory.maincent@...tlin.com>
> +
> +allOf:
> + - $ref: pse-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,pd69200
> + - microchip,pd69210
> + - microchip,pd69220
> +
> + reg:
> + maxItems: 1
> +
> + '#pse-cells':
> + const: 1
> +
> + ports-matrix:
> + description: each set of 48 logical ports can be assigned to one or two
> + physical ports. Each physical port is wired to a PD69204/8 PoE
> + manager. Using two different PoE managers for one RJ45 port
> + (logical port) is interesting for temperature dissipation.
> + This parameter describes the configuration of the port conversion
> + matrix that establishes the relationship between the 48 logical ports
> + and the available 96 physical ports. Unspecified logical ports will
> + be deactivated.
> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> + minItems: 1
> + maxItems: 48
> + items:
> + items:
> + - description: Logical port number
> + minimum: 0
> + maximum: 47
> + - description: Physical port number A (0xff for undefined)
> + oneOf:
> + - minimum: 0
> + maximum: 95
> + - const: 0xff
> + - description: Physical port number B (0xff for undefined)
> + oneOf:
> + - minimum: 0
> + maximum: 95
> + - const: 0xff
> +
> +unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> +
> +examples:
> + - |
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethernet-pse@3c {
> + compatible = "microchip,pd69200";
> + reg = <0x3c>;
> + #pse-cells = <1>;
> + ports-matrix = <0 2 5
> + 1 3 6
> + 2 0 0xff
> + 3 1 0xff>;
Hm... this will probably not scale. PSE is kind of PMIC for ethernet. I
has bunch of regulators which can be grouped to one more powerful
regulator. Since it is regulators, we will wont to represent them in a
system as regulators too. We will probably have physical, board
specific limitation, so we will need to describe regulator limits for
each separate channel.
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e3fd148d462e..b746684f3fd3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14235,6 +14235,12 @@ L: linux-serial@...r.kernel.org
> S: Maintained
> F: drivers/tty/serial/8250/8250_pci1xxxx.c
>
> +MICROCHIP PD692X0 PSE DRIVER
> +M: Kory Maincent <kory.maincent@...tlin.com>
> +L: netdev@...r.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml
> +
> MICROCHIP POLARFIRE FPGA DRIVERS
> M: Conor Dooley <conor.dooley@...rochip.com>
> R: Vladimir Georgiev <v.georgiev@...rotek.ru>
>
> --
> 2.25.1
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Powered by blists - more mailing lists