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Message-ID: <CAJM55Z-qc7gc0fO-K8byqvpOBjDxFD4dP57mFHuijvpOzBWObQ@mail.gmail.com>
Date: Mon, 4 Dec 2023 01:47:45 -0800
From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
To: Drew Fustini <dfustini@...libre.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Jisheng Zhang <jszhang@...nel.org>,
Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
Conor Dooley <conor@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: Jason Kridner <jkridner@...gleboard.org>,
Robert Nelson <robertcnelson@...gleboard.org>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v7 2/4] riscv: dts: thead: Add TH1520 mmc controllers and
sdhci clock
Drew Fustini wrote:
> Add node for the SDHCI fixed clock. Add mmc0 node for the first mmc
> controller instance which is typically connected to the eMMC device.
> Add mmc1 node for the second mmc controller instance which is typically
> connected to microSD slot.
>
> Signed-off-by: Drew Fustini <dfustini@...libre.com>
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index ba4d2c673ac8..af4fdcd82e0b 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -146,6 +146,13 @@ uart_sclk: uart-sclk-clock {
> #clock-cells = <0>;
> };
>
> + sdhci_clk: sdhci-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <198000000>;
> + clock-output-names = "sdhci_clk";
> + #clock-cells = <0>;
> + };
> +
> soc {
> compatible = "simple-bus";
> interrupt-parent = <&plic>;
> @@ -304,6 +311,24 @@ dmac0: dma-controller@...fc00000 {
> status = "disabled";
> };
>
> + mmc0: mmc@...7080000 {
> + compatible = "thead,th1520-dwcmshc";
> + reg = <0xff 0xe7080000 0x0 0x10000>;
> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sdhci_clk>;
> + clock-names = "core";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@...7090000 {
> + compatible = "thead,th1520-dwcmshc";
> + reg = <0xff 0xe7090000 0x0 0x10000>;
> + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&sdhci_clk>;
> + clock-names = "core";
> + status = "disabled";
> + };
> +
Hi Drew,
This doesn't seem to match the documentation shared here:
https://lore.kernel.org/linux-riscv/5f437109d2be2b8843f549a661054a2e3ec0d66e.camel@xry111.site/
>From the TH1520 System User Manual.pdf in there, I'd expect something like
emmc: mmc@...7080000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7080000 0x0 0x10000>;
...
};
sdio0: mmc@...7090000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe7090000 0x0 0x10000>;
...
};
sdio1: mmc@...70a0000 {
compatible = "thead,th1520-dwcmshc";
reg = <0xff 0xe70a0000 0x0 0x10000>;
...
};
/Emil
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