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Message-ID: <20231204100950.28712-2-quic_kriskura@quicinc.com>
Date: Mon, 4 Dec 2023 15:39:45 +0530
From: Krishna Kurapati <quic_kriskura@...cinc.com>
To: Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Wesley Cheng <quic_wcheng@...cinc.com>,
Conor Dooley <conor+dt@...nel.org>,
Johan Hovold <johan@...nel.org>,
<cros-qcom-dts-watchers@...omium.org>
CC: <linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<quic_ppratap@...cinc.com>, <quic_jackp@...cinc.com>,
Krishna Kurapati <quic_kriskura@...cinc.com>
Subject: [PATCH v2 1/6] dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings
The high speed related interrupts present on QC targets are as follows:
dp/dm irq's
These IRQ's directly reflect changes on the DP/DM pads of the SoC. These
are used as wakeup interrupts only on SoCs with non-QUSB2 targets with
exception of SDM670/SDM845/SM6350.
qusb2_phy irq
SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a
single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL
register. The required DPSE/DMSE configuration is done in
QUSB2PHY_INTR_CTRL register of phy address space.
hs_phy_irq
This is completely different from the above two and is present on all
targets with exception of a few IPQ ones. The interrupt is not enabled by
default and its functionality is mutually exclusive of qusb2_phy on QUSB
targets and DP/DM on femto phy targets.
The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq"
when they should have been "qusb2_phy_irq". On Femto phy targets, the
"hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event",
neither of which would never be triggered directly are non-functional
currently. The implementation tries to clean up this issue by addressing
the discrepencies involved and fixing the hs_phy_irq's in respective DT's.
Classify interrupts based on whether qusb2_phy interrupt is used or
{dp/dm}_hs_phy_irq is used and whether hs_phy_irq is present or not.
Signed-off-by: Krishna Kurapati <quic_kriskura@...cinc.com>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 147 +++++++-----------
1 file changed, 58 insertions(+), 89 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index 3ec62027f663..94deef765ec3 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -98,12 +98,30 @@ properties:
- const: apps-usb
interrupts:
- minItems: 1
- maxItems: 4
+ description: |
+ Different types of interrupts are used based on HS phy used on target::
+ - qusb2_phy:: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
+ expose only a single IRQ whose behavior can be modified
+ by the QUSB2PHY_INTR_CTRL register. The required DPSE/
+ DMSE configuration is done in QUSB2PHY_INTR_CTRL register
+ of phy address space.
+ - {dp/dm}_hs_phy_irq:: These IRQ's directly reflect changes on the DP/
+ DM pads of the SoC. These are used for wakeup
+ only on SoCs with non-QUSBb2 targets with
+ exception of SDM670/SDM845/SM6350.
+ - ss_phy_irq:: When in super speed mode of operation, interrupts are
+ received when a wakeup event is received on ss_phy_irq.
+ - hs_phY_irq:: Apart from DP/DM/QUSB2 Phy interrupts, there is
+ hs_phy_irq which is not triggered by default and its
+ functionality is mutually exclusive to that of
+ {dp/dm}_hs_phy_irq and qusb2_phy_irq.
+ - pwr_event:: Used for wakeup based on other power events.
+ minItems: 2
+ maxItems: 5
interrupt-names:
- minItems: 1
- maxItems: 4
+ minItems: 2
+ maxItems: 5
qcom,select-utmi-as-pipe-clk:
description:
@@ -359,116 +377,54 @@ allOf:
compatible:
contains:
enum:
- - qcom,ipq4019-dwc3
+ - qcom,ipq5018-dwc3
- qcom,ipq6018-dwc3
- - qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
- - qcom,msm8994-dwc3
- - qcom,qcs404-dwc3
- - qcom,sc7180-dwc3
- - qcom,sdm670-dwc3
- - qcom,sdm845-dwc3
- - qcom,sdx55-dwc3
- - qcom,sdx65-dwc3
- - qcom,sdx75-dwc3
- - qcom,sm4250-dwc3
- - qcom,sm6350-dwc3
- - qcom,sm8150-dwc3
- - qcom,sm8250-dwc3
- - qcom,sm8350-dwc3
- - qcom,sm8450-dwc3
- - qcom,sm8550-dwc3
- - qcom,sm8650-dwc3
+ - qcom,msm8953-dwc3
+ - qcom,msm8998-dwc3
+ - qcom,qcm2290-dwc3
then:
properties:
- interrupts:
- items:
- - description: The interrupt that is asserted
- when a wakeup event is received on USB2 bus.
- - description: The interrupt that is asserted
- when a wakeup event is received on USB3 bus.
- - description: Wakeup event on DM line.
- - description: Wakeup event on DP line.
interrupt-names:
items:
- - const: hs_phy_irq
- - const: ss_phy_irq
- - const: dm_hs_phy_irq
- - const: dp_hs_phy_irq
+ - const: pwr_event
+ - const: qusb2_phy
+ - const: ss_phy_irq (optional)
- if:
properties:
compatible:
contains:
enum:
- - qcom,msm8953-dwc3
- qcom,msm8996-dwc3
- - qcom,msm8998-dwc3
+ - qcom,qcs404-dwc3
+ - qcom,sdm660-dwc3
- qcom,sm6115-dwc3
- qcom,sm6125-dwc3
then:
properties:
- interrupts:
- maxItems: 2
interrupt-names:
items:
+ - const: pwr_event
- const: hs_phy_irq
- - const: ss_phy_irq
+ - const: qusb2_phy
+ - const: ss_phy_irq (optional)
- if:
properties:
compatible:
contains:
enum:
- - qcom,ipq5018-dwc3
- qcom,ipq5332-dwc3
- - qcom,sdm660-dwc3
- then:
- properties:
- interrupts:
- minItems: 1
- maxItems: 2
- interrupt-names:
- minItems: 1
- items:
- - const: hs_phy_irq
- - const: ss_phy_irq
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sc7280-dwc3
- then:
- properties:
- interrupts:
- minItems: 3
- maxItems: 4
- interrupt-names:
- minItems: 3
- items:
- - const: hs_phy_irq
- - const: dp_hs_phy_irq
- - const: dm_hs_phy_irq
- - const: ss_phy_irq
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- qcom,sc8280xp-dwc3
then:
properties:
- interrupts:
- maxItems: 4
interrupt-names:
items:
- const: pwr_event
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- - const: ss_phy_irq
+ - const: ss_phy_irq (optional)
- if:
properties:
@@ -476,18 +432,30 @@ allOf:
contains:
enum:
- qcom,sa8775p-dwc3
+ - qcom,sc7180-dwc3
+ - qcom,sc7280-dwc3
+ - qcom,sdm670-dwc3
+ - qcom,sdm845-dwc3
+ - qcom,sdx55-dwc3
+ - qcom,sdx65-dwc3
+ - qcom,sdx75-dwc3
+ - qcom,sm6350-dwc3
+ - qcom,sm6375-dwc3
+ - qcom,sm8150-dwc3
+ - qcom,sm8250-dwc3
+ - qcom,sm8350-dwc3
+ - qcom,sm8450-dwc3
+ - qcom,sm8550-dwc3
+ - qcom,sm8650-dwc3
then:
properties:
- interrupts:
- minItems: 3
- maxItems: 4
interrupt-names:
- minItems: 3
items:
- const: pwr_event
+ - const: hs_phy_irq
- const: dp_hs_phy_irq
- const: dm_hs_phy_irq
- - const: ss_phy_irq
+ - const: ss_phy_irq (optional)
additionalProperties: false
@@ -522,12 +490,13 @@ examples:
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
- <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event", "hs_phy_irq",
+ "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
--
2.42.0
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