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Message-Id: <fef3c174118174ae1d2ac9ff3c18850cf8605afa.1701691923.git.unicorn_wang@outlook.com>
Date: Mon, 4 Dec 2023 20:56:57 +0800
From: Chen Wang <unicornxw@...il.com>
To: aou@...s.berkeley.edu, chao.wei@...hgo.com, conor@...nel.org,
krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
palmer@...belt.com, paul.walmsley@...ive.com,
richardcochran@...il.com, robh+dt@...nel.org, sboyd@...nel.org,
devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
haijiao.liu@...hgo.com, xiaoguang.xing@...hgo.com,
guoren@...nel.org, jszhang@...nel.org, inochiama@...look.com,
samuel.holland@...ive.com
Cc: Chen Wang <unicorn_wang@...look.com>
Subject: [PATCH v3 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC
From: Chen Wang <unicorn_wang@...look.com>
Add clock generator node to device tree for SG2042, and enable clock for
uart.
Signed-off-by: Chen Wang <unicorn_wang@...look.com>
---
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 4 +
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 79 +++++++++++++++++++
2 files changed, 83 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index 49b4b9c2c101..0b3b3b2b0c64 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -14,6 +14,10 @@ chosen {
};
};
+&cgi {
+ clock-frequency = <25000000>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 93256540d078..ecc7758073af 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
#include "sg2042-cpus.dtsi"
@@ -18,6 +19,12 @@ aliases {
serial0 = &uart0;
};
+ cgi: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi";
+ #clock-cells = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -311,12 +318,84 @@ intc: interrupt-controller@...0000000 {
riscv,ndev = <224>;
};
+ sys_ctrl: system-controller@...0010000 {
+ compatible = "sophgo,sg2042-sysctrl";
+ reg = <0x70 0x30010000 0x0 0x1000>;
+ };
+
+ clkgen: clock-controller@...0012000 {
+ compatible = "sophgo,sg2042-clkgen";
+ reg = <0x70 0x30012000 0x0 0x1000>;
+ system-ctrl = <&sys_ctrl>;
+ #clock-cells = <1>;
+ clocks = <&cgi>;
+ assigned-clocks = \
+ <&clkgen DIV_CLK_FPLL_RP_CPU_NORMAL_1>,
+ <&clkgen DIV_CLK_FPLL_50M_A53>,
+ <&clkgen DIV_CLK_FPLL_TOP_RP_CMN_DIV2>,
+ <&clkgen DIV_CLK_FPLL_UART_500M>,
+ <&clkgen DIV_CLK_FPLL_AHB_LPC>,
+ <&clkgen DIV_CLK_FPLL_EFUSE>,
+ <&clkgen DIV_CLK_FPLL_TX_ETH0>,
+ <&clkgen DIV_CLK_FPLL_PTP_REF_I_ETH0>,
+ <&clkgen DIV_CLK_FPLL_REF_ETH0>,
+ <&clkgen DIV_CLK_FPLL_EMMC>,
+ <&clkgen DIV_CLK_FPLL_SD>,
+ <&clkgen DIV_CLK_FPLL_TOP_AXI0>,
+ <&clkgen DIV_CLK_FPLL_TOP_AXI_HSPERI>,
+ <&clkgen DIV_CLK_FPLL_AXI_DDR_1>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER1>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER2>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER3>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER4>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER5>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER6>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER7>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER8>,
+ <&clkgen DIV_CLK_FPLL_100K_EMMC>,
+ <&clkgen DIV_CLK_FPLL_100K_SD>,
+ <&clkgen DIV_CLK_FPLL_GPIO_DB>,
+ <&clkgen DIV_CLK_MPLL_RP_CPU_NORMAL_0>,
+ <&clkgen DIV_CLK_MPLL_AXI_DDR_0>;
+ assigned-clock-rates = \
+ <2000000000>,
+ <50000000>,
+ <1000000000>,
+ <500000000>,
+ <200000000>,
+ <25000000>,
+ <125000000>,
+ <50000000>,
+ <25000000>,
+ <100000000>,
+ <100000000>,
+ <100000000>,
+ <250000000>,
+ <1000000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <100000>,
+ <100000>,
+ <100000>,
+ <2000000000>,
+ <1000000000>;
+ };
+
uart0: serial@...0000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
+ clocks = <&clkgen GATE_CLK_UART_500M>,
+ <&clkgen GATE_CLK_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
--
2.25.1
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