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Message-ID: <bcafa1d8-1e19-6599-f5b2-16be3671bd19@ti.com>
Date: Tue, 5 Dec 2023 10:42:16 +0530
From: Ravi Gunasekaran <r-gunasekaran@...com>
To: Siddharth Vadapalli <s-vadapalli@...com>, <lpieralisi@...nel.org>,
<robh@...nel.org>, <kw@...ux.com>, <bhelgaas@...gle.com>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<vigneshr@...com>, <tjoseph@...ence.com>
CC: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <danishanwar@...com>,
<srk@...com>, <nm@...com>, Ravi Gunasekaran <r-gunasekaran@...com>
Subject: Re: [PATCH v13 3/5] PCI: j721e: Add per platform maximum lane
settings
On 11/28/23 11:14 AM, Siddharth Vadapalli wrote:
> From: Matt Ranostay <mranostay@...com>
>
> Various platforms have different maximum amount of lanes that can be
> selected. Add max_lanes to struct j721e_pcie to allow for detection of this
> which is needed to calculate the needed bitmask size for the possible lane
> count.
>
> Signed-off-by: Matt Ranostay <mranostay@...com>
> Signed-off-by: Achal Verma <a-verma1@...com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@...com>
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index 2c87e7728a65..63c758b14314 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -47,8 +47,6 @@ enum link_status {
>
> #define GENERATION_SEL_MASK GENMASK(1, 0)
>
> -#define MAX_LANES 2
> -
> struct j721e_pcie {
> struct cdns_pcie *cdns_pcie;
> struct clk *refclk;
> @@ -71,6 +69,7 @@ struct j721e_pcie_data {
> unsigned int quirk_disable_flr:1;
> u32 linkdown_irq_regfield;
> unsigned int byte_access_allowed:1;
> + unsigned int max_lanes;
> };
>
> static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
> @@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = {
> .quirk_retrain_flag = true,
> .byte_access_allowed = false,
> .linkdown_irq_regfield = LINK_DOWN,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j721e_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .linkdown_irq_regfield = LINK_DOWN,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j7200_pcie_rc_data = {
> @@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = {
> .quirk_detect_quiet_flag = true,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> .byte_access_allowed = true,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data j7200_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .quirk_detect_quiet_flag = true,
> .quirk_disable_flr = true,
> + .max_lanes = 2,
> };
>
> static const struct j721e_pcie_data am64_pcie_rc_data = {
> .mode = PCI_MODE_RC,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> .byte_access_allowed = true,
> + .max_lanes = 1,
> };
>
> static const struct j721e_pcie_data am64_pcie_ep_data = {
> .mode = PCI_MODE_EP,
> .linkdown_irq_regfield = J7200_LINK_DOWN,
> + .max_lanes = 1,
> };
>
> static const struct of_device_id of_j721e_pcie_match[] = {
> @@ -432,8 +437,10 @@ static int j721e_pcie_probe(struct platform_device *pdev)
> pcie->user_cfg_base = base;
>
> ret = of_property_read_u32(node, "num-lanes", &num_lanes);
> - if (ret || num_lanes > MAX_LANES)
> + if (ret || num_lanes > data->max_lanes) {
> + dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
> num_lanes = 1;
> + }
> pcie->num_lanes = num_lanes;
>
> if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@...com>
--
Regards,
Ravi
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