linux-kernel - RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs

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Date:   Tue, 5 Dec 2023 08:43:20 +0000
From:   James Tai [戴志峰] <james.tai@...ltek.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Marc Zyngier <maz@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: RE: [PATCH v2 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs

Hi Krzysztof,

>>>>>>> +  interrupts-extended:
>>>>>>
>>>>>> interrupts instead.
>>>>>>
>>>>>> Anyway, you must describe the items. Why this is not fixed but flexible?
>>>>>> Hardware has different number of pins? That's unlikely.
>>>>>>
>>>>> I will replace it with 'interrupts'. Since our Interrupt controller
>>>>> architecture doesn't involve multiple interrupt sources, using 'interrupts'
>>> should suffice.
>>>>>
>>>>
>>>> Due to changes in hardware design, some peripheral interrupts pin
>>>> initially
>>> connected to the Realtek interrupt controller were redirected to the GIC.
>>>> However, the associated fields and statuses in the Realtek interrupt
>>>> controller
>>> registers were not removed.
>>>> As a result, these interrupts cannot be cleared by peripheral
>>>> register, and their
>>> status clearing is still needing the Realtek interrupt controller driver to
>manage.
>>>>
>>>> That's why flexibility is necessary.
>>>
>>> This does not explain why this is not fixed per variant.
>>>
>>
>> Does the definition of "fixed" you mentioned refer to fixed interrupt pins? If
>> not, could you please give me an example and let me know what you mean by
>> "fixed"?
>
>Number of the interrupts per each device or variant should be strictly defined,
>not variable.

Thank you for your explanation.

The DHC platforms contain two interrupt controllers, each handling peripheral device interrupts in the two power domains. 
While each has a fixed IRQ numbers, the specific IRQ varies depending on the platform.

>Please wrap your emails according to mail netiquette.

I apologize for my rude way of asking the question. I will improve my expression.

Thank for your feedback.

Regards,
James