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Message-Id: <1fafcf1c70ee4e38847bac1379bcb4555a237505.1701768028.git.ysato@users.sourceforge.jp>
Date: Tue, 5 Dec 2023 18:45:36 +0900
From: Yoshinori Sato <ysato@...rs.sourceforge.jp>
To: linux-sh@...r.kernel.org
Cc: Yoshinori Sato <ysato@...rs.sourceforge.jp>,
Damien Le Moal <dlemoal@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
Thomas Gleixner <tglx@...utronix.de>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>,
Magnus Damm <magnus.damm@...il.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Rich Felker <dalias@...c.org>,
John Paul Adrian Glaubitz <glaubitz@...sik.fu-berlin.de>,
Lee Jones <lee@...nel.org>, Helge Deller <deller@....de>,
Heiko Stuebner <heiko@...ech.de>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Chris Morgan <macromorgan@...mail.com>,
Linus Walleij <linus.walleij@...aro.org>,
Randy Dunlap <rdunlap@...radead.org>,
Arnd Bergmann <arnd@...db.de>,
Hyeonggon Yoo <42.hyeyoo@...il.com>,
David Rientjes <rientjes@...gle.com>,
Vlastimil Babka <vbabka@...e.cz>, Baoquan He <bhe@...hat.com>,
Andrew Morton <akpm@...ux-foundation.org>,
Guenter Roeck <linux@...ck-us.net>,
Stephen Rothwell <sfr@...b.auug.org.au>,
Guo Ren <guoren@...nel.org>,
Javier Martinez Canillas <javierm@...hat.com>,
Azeem Shaikh <azeemshaikh38@...il.com>,
Palmer Dabbelt <palmer@...osinc.com>,
Bin Meng <bmeng@...ylab.org>,
Max Filippov <jcmvbkbc@...il.com>, Tom Rix <trix@...hat.com>,
Herve Codina <herve.codina@...tlin.com>,
Jacky Huang <ychuang3@...oton.com>,
Lukas Bulwahn <lukas.bulwahn@...il.com>,
Jonathan Corbet <corbet@....net>,
Biju Das <biju.das.jz@...renesas.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Sam Ravnborg <sam@...nborg.org>,
Michael Karcher <kernel@...rcher.dialup.fu-berlin.de>,
Sergey Shtylyov <s.shtylyov@....ru>,
Laurent Pinchart <laurent.pinchart+renesas@...asonboard.com>,
linux-ide@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-pci@...r.kernel.org, linux-serial@...r.kernel.org,
linux-fbdev@...r.kernel.org
Subject: [DO NOT MERGE v5 17/37] dt-bindings: interrupt-controller: renesas,sh7751-intc: Add json-schema
Renesas SH7751 INTC json-schema.
Signed-off-by: Yoshinori Sato <ysato@...rs.sourceforge.jp>
---
.../renesas,sh7751-intc.yaml | 105 ++++++++++++++++++
1 file changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
new file mode 100644
index 000000000000..9d05c10f5c32
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,sh7751-intc.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,sh7751-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas SH7751 Interrupt Controller
+
+maintainers:
+ - Yoshinori Sato <ysato@...rs.sourceforge.jp>
+
+properties:
+ compatible:
+ items:
+ - const: renesas,sh7751-intc
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: ICR
+ - const: INTPRI00
+
+ renesas,icr-irlm:
+ type: boolean
+ description: If true ICR.IRLM=1
+
+ renesas,ipr-map:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ IRQ to IPR mapping definition.
+ 1st - INTEVT
+ 2nd - Register
+ 3rd - bit index
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - interrupt-controller
+ - reg
+ - reg-names
+ - renesas,ipr-map
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/sh_intc.h>
+ shintc: interrupt-controller@...00000 {
+ compatible = "renesas,sh7751-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ reg = <0xffd00000 14>, <0xfe080000 128>;
+ reg-names = "ICR", "INTPRI00";
+ renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */
+ <0x2a0 IPRD IPR_B8>, /* IRL1 */
+ <0x300 IPRD IPR_B4>, /* IRL2 */
+ <0x360 IPRD IPR_B0>, /* IRL3 */
+ <0x400 IPRA IPR_B12>, /* TMU0 */
+ <0x420 IPRA IPR_B8>, /* TMU1 */
+ <0x440 IPRA IPR_B4>, /* TMU2 TNUI */
+ <0x460 IPRA IPR_B4>, /* TMU2 TICPI */
+ <0x480 IPRA IPR_B0>, /* RTC ATI */
+ <0x4a0 IPRA IPR_B0>, /* RTC PRI */
+ <0x4c0 IPRA IPR_B0>, /* RTC CUI */
+ <0x4e0 IPRB IPR_B4>, /* SCI ERI */
+ <0x500 IPRB IPR_B4>, /* SCI RXI */
+ <0x520 IPRB IPR_B4>, /* SCI TXI */
+ <0x540 IPRB IPR_B4>, /* SCI TEI */
+ <0x560 IPRB IPR_B12>, /* WDT */
+ <0x580 IPRB IPR_B8>, /* REF RCMI */
+ <0x5a0 IPRB IPR_B4>, /* REF ROVI */
+ <0x600 IPRC IPR_B0>, /* H-UDI */
+ <0x620 IPRC IPR_B12>, /* GPIO */
+ <0x640 IPRC IPR_B8>, /* DMAC DMTE0 */
+ <0x660 IPRC IPR_B8>, /* DMAC DMTE1 */
+ <0x680 IPRC IPR_B8>, /* DMAC DMTE2 */
+ <0x6a0 IPRC IPR_B8>, /* DMAC DMTE3 */
+ <0x6c0 IPRC IPR_B8>, /* DMAC DMAE */
+ <0x700 IPRC IPR_B4>, /* SCIF ERI */
+ <0x720 IPRC IPR_B4>, /* SCIF RXI */
+ <0x740 IPRC IPR_B4>, /* SCIF BRI */
+ <0x760 IPRC IPR_B4>, /* SCIF TXI */
+ <0x780 IPRC IPR_B8>, /* DMAC DMTE4 */
+ <0x7a0 IPRC IPR_B8>, /* DMAC DMTE5 */
+ <0x7c0 IPRC IPR_B8>, /* DMAC DMTE6 */
+ <0x7e0 IPRC IPR_B8>, /* DMAC DMTE7 */
+ <0xa00 INTPRI00 IPR_B0>, /* PCIC PCISERR */
+ <0xa20 INTPRI00 IPR_B4>, /* PCIC PCIDMA3 */
+ <0xa40 INTPRI00 IPR_B4>, /* PCIC PCIDMA2 */
+ <0xa60 INTPRI00 IPR_B4>, /* PCIC PCIDMA1 */
+ <0xa80 INTPRI00 IPR_B4>, /* PCIC PCIDMA0 */
+ <0xaa0 INTPRI00 IPR_B4>, /* PCIC PCIPWON */
+ <0xac0 INTPRI00 IPR_B4>, /* PCIC PCIPWDWN */
+ <0xae0 INTPRI00 IPR_B4>, /* PCIC PCIERR */
+ <0xb00 INTPRI00 IPR_B8>, /* TMU3 */
+ <0xb80 INTPRI00 IPR_B12>; /* TMU4 */
+ };
+...
--
2.39.2
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