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Message-ID: <20231206-sizzling-whoopee-9e2a6755cd05@spud>
Date: Wed, 6 Dec 2023 16:45:18 +0000
From: Conor Dooley <conor@...nel.org>
To: Sia Jee Heng <jeeheng.sia@...rfivetech.com>
Cc: kernel@...il.dk, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, krzk@...nel.org,
conor+dt@...nel.org, paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, daniel.lezcano@...aro.org,
tglx@...utronix.de, anup@...infault.org,
gregkh@...uxfoundation.org, jirislaby@...nel.org,
michal.simek@....com, michael.zhu@...rfivetech.com,
drew@...gleboard.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
leyfoon.tan@...rfivetech.com
Subject: Re: [PATCH v3 0/6] Initial device tree support for StarFive JH8100
SoC
On Fri, Dec 01, 2023 at 08:14:04PM +0800, Sia Jee Heng wrote:
> StarFive JH8100 SoC consists of 4 RISC-V performance Cores (Dubhe-90) and
> 2 RISC-V energy efficient cores (Dubhe-80). It also features various
> interfaces such as DDR4, Gbit-Ether, CAN, USB 3.2, SD/MMC, etc., making it
> ideal for high-performance computing scenarios.
>
> This patch series introduces initial SoC DTSI support for the StarFive
> JH8100 SoC. The relevant dt-binding documentation has been updated
> accordingly. Below is the list of IP blocks added in the initial SoC DTSI,
> which can be used for booting via initramfs on FPGA:
This all seems okay to me. I'll need an ack from Emil though before I
can pick it up.
Thanks,
Conor.
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